(nuttx) branch master updated: arm64: fix tpidr maybe null

[xiaoxiang]

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xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git


The following commit(s) were added to refs/heads/master by this push:
     new 2886fddc0f arm64: fix tpidr maybe null
2886fddc0f is described below

commit 2886fddc0f17794067c739c79f02d1ee79052f51
Author: hujun5 <huj...@xiaomi.com>
AuthorDate: Wed Dec 25 16:51:33 2024 +0800

    arm64: fix tpidr maybe null
    
    Before the MPU initialization, the up_update_task(this_cpu()) function is 
called at a time when hardware cache coherency is not yet enabled.
    In certain critical scenarios, Core 1 reads a zero value for tcb from the 
global variable g_assignedtask and stores this zero value into the tpidr
    register. This results in subsequent interrupt handlers reading a zero tcb, 
causing an exception.
    
    Signed-off-by: hujun5 <huj...@xiaomi.com>
---
 arch/arm64/src/common/arm64_cpustart.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/src/common/arm64_cpustart.c 
b/arch/arm64/src/common/arm64_cpustart.c
index 25a25eaa19..00876cbaea 100644
--- a/arch/arm64/src/common/arm64_cpustart.c
+++ b/arch/arm64/src/common/arm64_cpustart.c
@@ -217,12 +217,6 @@ int up_cpu_start(int cpu)
 
 void arm64_boot_secondary_c_routine(void)
 {
-  struct tcb_s *tcb = current_task(this_cpu());
-
-  /* Init idle task to percpu reg */
-
-  up_update_task(tcb);
-
 #ifdef CONFIG_ARCH_HAVE_MPU
   arm64_mpu_init(false);
 #endif
@@ -231,6 +225,14 @@ void arm64_boot_secondary_c_routine(void)
   arm64_mmu_init(false);
 #endif
 
+  /* We need to confirm that current_task has been initialized. */
+
+  while (!current_task(this_cpu()));
+
+  /* Init idle task to percpu reg */
+
+  up_update_task(current_task(this_cpu()));
+
   arm64_gic_secondary_init();
 
   arm64_smp_init_top();