jlaitine opened a new pull request, #15878:
URL: https://github.com/apache/nuttx/pull/15878
## Summary
- Move PLIC interrupt enable and disable functions into mpfs_plic.c
- Remove race conditions between irq enable/disable by adding spinlock
- An interrupt may trigger on one hart in the middle of enabling the
interrupts - then the interrupt handler might call up_disable_irq.
- When enabling interrupts, always clear pending interrupt:
A pending interrupt would trigger immediately when enabling the interrupt
source, but this is not expected. The interrupt source is level sensitive, so
it should only trigger if the source is active at the time when it is enabled.
Not if it was active sometime in the past but inactive at the time when the IRQ
is enabled.
The issue becomes with devices where the interrupt source (the line
connected to the PLIC) can't be masked / controlled, but the IRQ itself needs
to be just enabled/disabled at the times when you know the line status is
valid. If the source toggles while the PLIC interrupt is disabled or the
interrupt is disabled when the line is active, the interrupt would always
trigger right away when next time enabling the IRQ even if the irq source is
inactive at that time.
The way how PLIC is designed is such that a pending interrupt can't be
cleared. Clearing a pending interrupt can only be done by handling the
interrupt (claiming it, and then acking it). Claiming an interrupt is only
legal when the interrupt is enabled.
The issue with such pending interrupts is now handled as follows:
1. When enabling interrupts, check if there is a pending one, and do the
following steps for the pending irq
2. Raise the priority of the pending interrupt to the maximum. This moves
the pending irq to the head of the claim queue in PLIC when the source is
enabled
3. Enable the PLIC irq source for the pending one on the current hart (the
irq suorce needs to be enabled for steps 4. and 5)
4. Claim the next interrupt from PLIC (this is now always the pending one,
due to 2. and no other hart has claimed it since all sources on other harts are
disabled)
5. Ack the pending IRQ
6. Lower the PLIC IRQ priority back to normal
7. Proceed on enabling the interrupts on the other harts.
## Impact
Impacts only MPFS targets. Fixes issues when trying to disable PLIC
interrupt from interrupt handler, and issues of receiving an extra interrupt
when enabling interrupts.
## Testing
Desk-tested on a custom MPFS board and on a Microchip MPFS Icicle board,
using CONFIG_BUILD_FLAT and both CONFIG_SMP=y and CONFIG_SMP=n
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