(nuttx) branch master updated: arch/arm/rp23xx: Fix PWM registers access

[xiaoxiang]

This is an automated email from the ASF dual-hosted git repository.

xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git


The following commit(s) were added to refs/heads/master by this push:
     new 5ddc67b129 arch/arm/rp23xx: Fix PWM registers access
5ddc67b129 is described below

commit 5ddc67b12919d4fdc1bd3178e43a7fc93eb90e9b
Author: Serg Podtynnyi <s...@podtynnyi.com>
AuthorDate: Tue Apr 15 12:59:51 2025 +0700

    arch/arm/rp23xx: Fix PWM registers access
    
    Fix offset alignment and correct the PWM enable register name
    
    Signed-off-by: Serg Podtynnyi <s...@podtynnyi.com>
---
 arch/arm/src/rp23xx/hardware/rp23xx_pwm.h | 10 +++++-----
 arch/arm/src/rp23xx/rp23xx_pwm.c          |  4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/src/rp23xx/hardware/rp23xx_pwm.h 
b/arch/arm/src/rp23xx/hardware/rp23xx_pwm.h
index 132f5cf351..50a01a1c2c 100644
--- a/arch/arm/src/rp23xx/hardware/rp23xx_pwm.h
+++ b/arch/arm/src/rp23xx/hardware/rp23xx_pwm.h
@@ -35,11 +35,11 @@
 
 /* Register offsets *********************************************************/
 
-#define RP23XX_PWM_CSR_OFFSET(n)  (0x000000 + (n) * 14) /* PWM control and 
status register */
-#define RP23XX_PWM_DIV_OFFSET(n)  (0x000004 + (n) * 14) /* PWM clock divisor 
register */
-#define RP23XX_PWM_CTR_OFFSET(n)  (0x000008 + (n) * 14) /* PWM counter 
register */
-#define RP23XX_PWM_CC_OFFSET(n)   (0x00000c + (n) * 14) /* PWM compare 
register */
-#define RP23XX_PWM_TOP_OFFSET(n)  (0x000010 + (n) * 14) /* PWM wrap value 
register */
+#define RP23XX_PWM_CSR_OFFSET(n)  (0x000000 + (n) * 20) /* PWM control and 
status register */
+#define RP23XX_PWM_DIV_OFFSET(n)  (0x000004 + (n) * 20) /* PWM clock divisor 
register */
+#define RP23XX_PWM_CTR_OFFSET(n)  (0x000008 + (n) * 20) /* PWM counter 
register */
+#define RP23XX_PWM_CC_OFFSET(n)   (0x00000c + (n) * 20) /* PWM compare 
register */
+#define RP23XX_PWM_TOP_OFFSET(n)  (0x000010 + (n) * 20) /* PWM wrap value 
register */
 #define RP23XX_PWM_EN_OFFSET     0x0000f0               /* PWM enable register 
*/
 #define RP23XX_PWM_INTR_OFFSET    0x0000f4              /* PWM raw interrupt 
register */
 #define RP23XX_PWM_IRQ0_INTE_OFFSET    0x0000f8         /* PWM interrupt 
enable register */
diff --git a/arch/arm/src/rp23xx/rp23xx_pwm.c b/arch/arm/src/rp23xx/rp23xx_pwm.c
index 87e2608442..cdb4b5ba3c 100644
--- a/arch/arm/src/rp23xx/rp23xx_pwm.c
+++ b/arch/arm/src/rp23xx/rp23xx_pwm.c
@@ -572,7 +572,7 @@ static inline void set_enabled(struct 
rp23xx_pwm_lowerhalf_s  * priv)
 {
   irqstate_t flags = enter_critical_section();
 
-  modreg32(1 << priv->num, 1 << priv->num,  RP23XX_PWM_ENA);
+  modreg32(1 << priv->num, 1 << priv->num,  RP23XX_PWM_EN);
 
   leave_critical_section(flags);
 }
@@ -592,7 +592,7 @@ static inline void clear_enabled(struct 
rp23xx_pwm_lowerhalf_s  * priv)
 {
   irqstate_t flags = enter_critical_section();
 
-  modreg32(0, 1 << priv->num, RP23XX_PWM_ENA);
+  modreg32(0, 1 << priv->num, RP23XX_PWM_EN);
 
   leave_critical_section(flags);
 }