raiden00pl commented on code in PR #16500: URL: https://github.com/apache/nuttx/pull/16500#discussion_r2137212888
########## arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h: ########## @@ -240,27 +277,48 @@ #define ADC_CHSELR_CHSEL16 (1 << 16) /* Select channel 16 */ #define ADC_CHSELR_CHSEL17 (1 << 17) /* Select channel 17 */ #define ADC_CHSELR_CHSEL18 (1 << 18) /* Select channel 18 */ -#define ADC_CHSELR_CHSEL(ch) (1 << ch) +#define ADC_CHSELR_CHSEL(ch) (1 << (ch)) + +/* ADC channel selection alternate register + * Enabled when CHSELRMOD = 1 in ADC_CFGR1 + */ + +#if defined(CONFIG_ARCH_CHIP_STM32G0) +# define ADC_CHSELR_ALT_SQN(sqn, ch) ((ch) << (((sqn) - 1) * 4)) /* sqn = [0..8], ch = [0..14] */ +#endif #define ADC_DR_RDATA_SHIFT (0) #define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) +/* Analog watchdog 2/3 configuration register */ + +#define ADC_AWDXCR_AWDXCHN(ch) (1 << (ch)) /* ch = [0..18] */ + +/* Calibration factor register */ + +#define ADC_CALFACT_CALFACT_SHIFT (0) +#define ADC_CALFACT_CALFACT_MASK (0x7f << ADC_CALFACT_CALFACT_SHIFT) + /* Common configuration register */ -#ifdef HAVE_ADC_VLCD -# define ADC_CCR_PRESC_SHIFT (18) /* ADC Prescaler */ -# define ADC_CCR_PRESC_MASK (0xf << ADC_CCR_PRESC_SHIFT) -#endif +#define ADC_CCR_PRESC_SHIFT (18) /* ADC Prescaler */ +#define ADC_CCR_PRESC_MASK (0xf << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_2 (1 << ADC_CCR_PRESC_SHIFT) Review Comment: can we use the same names as in stm32h7? `ADC_CCR_PRESC_NOT_DIV`, `ADC_CCR_PRESC_DIV2` etc. It's more popular (stm32g4 definitions should be fixed someday) -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org
