gpoulios commented on code in PR #16729:
URL: https://github.com/apache/nuttx/pull/16729#discussion_r2209184982
##########
drivers/misc/optee.c:
##########
@@ -345,6 +346,10 @@ optee_shm_to_page_list(FAR struct optee_shm *shm, FAR
uintptr_t *list_pa)
*list_pa = optee_va_to_pa(list) | pgoff;
}
+#ifndef CONFIG_ARCH_USE_MMU
Review Comment:
> but MMU is still enable, otherwise the code doesn't need program MMU
related registers.
Sorry I don't follow. Cache maintenance code I added is guarded around "MMU
not being enabled".
> I never saw Cortex-A chip doesn't enable MMU in proudction [...]
We're running a custom bootloader that has it disabled to reduce size.
https://github.com/apache/nuttx/blob/a754b73e4c5faf50b30e9cf84de54d5bb99c3b45/arch/arm64/src/imx9/imx9_boot.c#L182-L186
> [...] since the cachable configuration come from MMU entry and disable
cache forcely when MMU is off.
You mean overall cache config (`SCTLR_C_BIT`) is forced off when MMU is off?
That's not what I see in the code but it doesn't really matter for the purposes
of this discussion.
> The real difference is whether config MMU to flat virtual address
space(flat build) or overlapped virtual address space(kernel build).
No, I explained what my tests show, and what I think the root cause is (see
my previous message). Difference is when the MMU is off vs on, **not** when I
build flat vs kernel.
> But either config is the pure software favorite, I am wondering why it
impact the cache coherence between normal and secure world.
Is my previous message not a satisfactory explanation or did you just miss
it?
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: [email protected]
For queries about this service, please contact Infrastructure at:
[email protected]
