Re: [PR] arch/arm/armv8-r: fix multicore gicv3 init issue [nuttx]

[via GitHub]

wangchdo commented on code in PR #16892:
URL: https://github.com/apache/nuttx/pull/16892#discussion_r2296893090


##########
arch/arm/src/armv8-r/arm_doirq.c:
##########
@@ -113,14 +113,32 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
 
 void up_irqinitialize(void)
 {
-  /* The following operations need to be atomic, but since this function is
-   * called early in the initialization sequence, we expect to have exclusive
-   * access to the GIC.
-   */
+#ifdef CONFIG_SMP
+  static volatile uint32_t gicd_ready = 0;
+
+  if (up_cpu_index() == 0)
+    {
+#endif
+      /* Initialize GICD、GICRD and GIC cpu interface for cpu0  */
+
+      arm_gic_initialize();
+#ifdef CONFIG_SMP
+      gicd_ready = 1;
+    }
+  else
+    {
+      /* For other CPUs, we will only initialize GICRD and
+       * GIC cpu interface.
+       */
 
-  /* Initialize the Generic Interrupt Controller (GIC) for CPU0 */
+      while (gicd_ready == 0)

Review Comment:
   Some SoC may release all the cpus simultaneously after power on, while let 
the software to do the synchronization.  
   
   By the way, gic init was called by nuttx kernel in nx_start, which is also 
probably called by some cpus simultaneously while cpu0 is doing it, because 
cpu0 tend to do more stuff in initialization after releasing other cpus.



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