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The following commit(s) were added to refs/heads/master by this push:
new 251b19272fe arch/arm/src/stm32f0l0g0: add FLASH support for STM32C0
251b19272fe is described below
commit 251b19272fef71144635935f96fe2da132969b9d
Author: raiden00pl <[email protected]>
AuthorDate: Wed Oct 1 14:07:28 2025 +0200
arch/arm/src/stm32f0l0g0: add FLASH support for STM32C0
Add FLASH support for STM32C0 based on STM32G0 FLASH driver.
FLASH support is identical for these two, except that the STM32G0 can
support
dual bank, which is not available in the STM32C0.
Signed-off-by: raiden00pl <[email protected]>
---
arch/arm/src/stm32f0l0g0/Kconfig | 43 ++++++++
arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h | 115 ++++++++++++++++++++-
arch/arm/src/stm32f0l0g0/stm32_flash.c | 4 +-
.../{stm32g0_flash.c => stm32g0c0_flash.c} | 37 ++++---
4 files changed, 180 insertions(+), 19 deletions(-)
diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig
index ae2f6954add..823254a704c 100644
--- a/arch/arm/src/stm32f0l0g0/Kconfig
+++ b/arch/arm/src/stm32f0l0g0/Kconfig
@@ -909,166 +909,207 @@ config ARCH_CHIP_STM32L073RZ
config ARCH_CHIP_STM32C051D8
bool "STM32C051D8"
select ARCH_CHIP_STM32C051XX
+ select STM32F0L0G0_FLASH_CONFIG_8
config ARCH_CHIP_STM32C051F6
bool "STM32C051F6"
select ARCH_CHIP_STM32C051XX
+ select STM32F0L0G0_FLASH_CONFIG_6
config ARCH_CHIP_STM32C051F8
bool "STM32C051F8"
select ARCH_CHIP_STM32C051XX
+ select STM32F0L0G0_FLASH_CONFIG_8
config ARCH_CHIP_STM32C051G6
bool "STM32C051G6"
select ARCH_CHIP_STM32C051XX
+ select STM32F0L0G0_FLASH_CONFIG_6
config ARCH_CHIP_STM32C051G8
bool "STM32C051G8"
select ARCH_CHIP_STM32C051XX
+ select STM32F0L0G0_FLASH_CONFIG_8
config ARCH_CHIP_STM32C051K6
bool "STM32C051K6"
select ARCH_CHIP_STM32C051XX
+ select STM32F0L0G0_FLASH_CONFIG_6
config ARCH_CHIP_STM32C051K8
bool "STM32C051K8"
select ARCH_CHIP_STM32C051XX
+ select STM32F0L0G0_FLASH_CONFIG_8
config ARCH_CHIP_STM32C051C6
bool "STM32C051C6"
select ARCH_CHIP_STM32C051XX
+ select STM32F0L0G0_FLASH_CONFIG_6
config ARCH_CHIP_STM32C051C8
bool "STM32C051C8"
select ARCH_CHIP_STM32C051XX
+ select STM32F0L0G0_FLASH_CONFIG_8
config ARCH_CHIP_STM32C071F8
bool "STM32C071F8"
select ARCH_CHIP_STM32C071XX
+ select STM32F0L0G0_FLASH_CONFIG_8
config ARCH_CHIP_STM32C071FB
bool "STM32C071FB"
select ARCH_CHIP_STM32C071XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C071G8
bool "STM32C071G8"
select ARCH_CHIP_STM32C071XX
+ select STM32F0L0G0_FLASH_CONFIG_8
config ARCH_CHIP_STM32C071GB
bool "STM32C071GB"
select ARCH_CHIP_STM32C071XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C071K8
bool "STM32C071K8"
select ARCH_CHIP_STM32C071XX
+ select STM32F0L0G0_FLASH_CONFIG_8
config ARCH_CHIP_STM32C071KB
bool "STM32C071KB"
select ARCH_CHIP_STM32C071XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C071C8
bool "STM32C071C8"
select ARCH_CHIP_STM32C071XX
+ select STM32F0L0G0_FLASH_CONFIG_8
config ARCH_CHIP_STM32C071CB
bool "STM32C071CB"
select ARCH_CHIP_STM32C071XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C071R8
bool "STM32C071R8"
select ARCH_CHIP_STM32C071XX
+ select STM32F0L0G0_FLASH_CONFIG_8
config ARCH_CHIP_STM32C071RB
bool "STM32C071RB"
select ARCH_CHIP_STM32C071XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C091FB
bool "STM32C091FB"
select ARCH_CHIP_STM32C091XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C091FC
bool "STM32C091FC"
select ARCH_CHIP_STM32C091XX
+ select STM32F0L0G0_FLASH_CONFIG_C
config ARCH_CHIP_STM32C091EC
bool "STM32C091EC"
select ARCH_CHIP_STM32C091XX
+ select STM32F0L0G0_FLASH_CONFIG_C
config ARCH_CHIP_STM32C091GB
bool "STM32C091GB"
select ARCH_CHIP_STM32C091XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C091GC
bool "STM32C091GC"
select ARCH_CHIP_STM32C091XX
+ select STM32F0L0G0_FLASH_CONFIG_C
config ARCH_CHIP_STM32C091KB
bool "STM32C091KB"
select ARCH_CHIP_STM32C091XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C091KC
bool "STM32C091KC"
select ARCH_CHIP_STM32C091XX
+ select STM32F0L0G0_FLASH_CONFIG_C
config ARCH_CHIP_STM32C091CB
bool "STM32C091CB"
select ARCH_CHIP_STM32C091XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C091CC
bool "STM32C091CC"
select ARCH_CHIP_STM32C091XX
+ select STM32F0L0G0_FLASH_CONFIG_C
config ARCH_CHIP_STM32C091RB
bool "STM32C091RB"
select ARCH_CHIP_STM32C091XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C091RC
bool "STM32C091RC"
select ARCH_CHIP_STM32C091XX
+ select STM32F0L0G0_FLASH_CONFIG_C
config ARCH_CHIP_STM32C092FB
bool "STM32C092FB"
select ARCH_CHIP_STM32C092XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C092FC
bool "STM32C092FC"
select ARCH_CHIP_STM32C092XX
+ select STM32F0L0G0_FLASH_CONFIG_C
config ARCH_CHIP_STM32C092EC
bool "STM32C092EC"
select ARCH_CHIP_STM32C092XX
+ select STM32F0L0G0_FLASH_CONFIG_C
config ARCH_CHIP_STM32C092GB
bool "STM32C092GB"
select ARCH_CHIP_STM32C092XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C092GC
bool "STM32C092GC"
select ARCH_CHIP_STM32C092XX
+ select STM32F0L0G0_FLASH_CONFIG_C
config ARCH_CHIP_STM32C092KB
bool "STM32C092KB"
select ARCH_CHIP_STM32C092XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C092KC
bool "STM32C092KC"
select ARCH_CHIP_STM32C092XX
+ select STM32F0L0G0_FLASH_CONFIG_C
config ARCH_CHIP_STM32C092CB
bool "STM32C092CB"
select ARCH_CHIP_STM32C092XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C092CC
bool "STM32C092CC"
select ARCH_CHIP_STM32C092XX
+ select STM32F0L0G0_FLASH_CONFIG_C
config ARCH_CHIP_STM32C092RB
bool "STM32C092RB"
select ARCH_CHIP_STM32C092XX
+ select STM32F0L0G0_FLASH_CONFIG_B
config ARCH_CHIP_STM32C092RC
bool "STM32C092RC"
select ARCH_CHIP_STM32C092XX
+ select STM32F0L0G0_FLASH_CONFIG_C
endchoice # ST STM32F0/L0/G0/C0 Chip Selection
@@ -1210,6 +1251,7 @@ config STM32F0L0G0_STM32G0
select STM32F0L0G0_HAVE_TIM16
select STM32F0L0G0_HAVE_TIM17
select STM32F0L0G0_HAVE_I2C2
+ select ARCH_HAVE_PROGMEM
config STM32F0L0G0_STM32L0
bool
@@ -1235,6 +1277,7 @@ config STM32F0L0G0_STM32C0
select STM32F0L0G0_HAVE_TIM14
select STM32F0L0G0_HAVE_TIM16
select STM32F0L0G0_HAVE_TIM17
+ select ARCH_HAVE_PROGMEM
config STM32F0L0G0_STM32F03X
bool
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h
b/arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h
index 2d7480429db..dfcdb1e5e13 100644
--- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h
@@ -87,6 +87,119 @@
#define FLASH_ACR_DBGSWEN (1 << 18) /* Bit 18: Debug access software
enable */
/* Bits 19-31: Reserved */
-/* TODO */
+/* Flash Status Register (SR) */
+
+#define FLASH_SR_EOP (1) /* Bit 0: End of operation */
+#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
+ /* Bit 2: Reserved */
+#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */
+#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection
error */
+#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment
error */
+#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */
+#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence
error */
+#define FLASH_SR_MISSERR (1 << 8) /* Bit 8: Fast programming data
miss error */
+#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming
error */
+ /* Bits 10-13: Reserved */
+#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */
+#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option and
engineering bits loading validity error */
+#define FLASH_SR_BSY1 (1 << 16) /* Bit 16: Busy */
+ /* Bit 17: Reserved */
+#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Programming or erase
configuration busy */
+ /* Bits 19-31: Reserved */
+
+/* Flash Control Register (CR) */
+
+#define FLASH_CR_PG (1) /* Bit 0: Flash memory
programming enable */
+#define FLASH_CR_PER (1 << 1) /* Bit 1: Page erase enable */
+#define FLASH_CR_MER1 (1 << 2) /* Bit 2: Mass erase */
+#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number
selection */
+#define FLASH_CR_PNB_MASK (0x7f << FLASH_CR_PNB_SHIFT)
+# define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT)
+
+#define FLASH_CR_STRT (1 << 16) /* Bit 16: Start erase
operation */
+#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Start of
modification of option bytes */
+#define FLASH_CR_FSTPG (1 << 18) /* Bit 18: Fast programming
enable */
+ /* Bits 19-23: Reserved */
+#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End-of-operation
interrupt enable */
+#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt
enable */
+#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error
interrupt enable */
+#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option byte load
launch */
+#define FLASH_CR_SEC_PROT (1 << 28) /* Bit 28: Securable memory
area protection enable */
+ /* Bit 29: Reserved */
+#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Options Lock */
+#define FLASH_CR_LOCK (1 << 31) /* Bit 31: FLASH_CR Lock */
+
+/* Flash Option Register (OPTR) */
+
+#define FLASH_OPTR_RDP_SHIFT (0)
+#define FLASH_OPTR_RDP_MASK (0xff << FLASH_OPTR_RDP_SHIFT)
+#define FLASH_OPTR_BOR_EN (1 << 8) /* Brown out reset enable */
+#define FLASH_OPTR_BORR_LEV_SHIFT (9) /* BOR threshold at rising Vdd
supply */
+#define FLASH_OPTR_BORR_LEV_MASK (0x3 << FLASH_OPTR_BORR_LEV_SHIFT)
+#define FLASH_OPTR_BORF_LEV_SHIFT (11) /* BOR thresholda t falling Vdd
supply */
+#define FLASH_OPTR_BORF_LEV_MASK (0x3 << FLASH_OPTR_BORF_LEV_SHIFT)
+#define FLASH_OPTR_NRST_STOP (1 << 13)
+#define FLASH_OPTR_NRST_STDBY (1 << 14)
+#define FLASH_OPTR_NRSTS_SHDW (1 << 15)
+#define FLASH_OPTR_IDWG_SW (1 << 16) /* Bit 16: Independent watchdog
selection */
+#define FLASH_OPTR_IDWG_STOP (1 << 17) /* Bit 17: Independent watchdog
counter freeze in stop mode */
+#define FLASH_OPTR_IDWG_STDBY (1 << 18) /* Bit 18: Independent watchdog
counter freeze in Standby mode */
+#define FLASH_OPTR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog
selection */
+ /* Bit 20: Reserved */
+#define FLASH_OPTR_HSE_NOT_REMAPPED (1 << 21) /* Bit 21: HSE remapping
enable/disable */
+#define FLASH_OPTR_RAM_PARITY_CHECK (1 << 22) /* Bit 22: SRAM parity check
control */
+#define FLASH_OPTR_SECURE_MUXING_EN (1 << 23) /* Bit 23: Multiple-bonding
security */
+ /* Bit 23: Reserved */
+#define FLASH_OPTR_NBOOT_SEL (1 << 24) /* Bit 24: BOOT0 signal source
selection */
+#define FLASH_OPTR_NBOOT1 (1 << 25) /* Bit 25: NBOOT1 boot
configuration */
+#define FLASH_OPTR_NBOOT0 (1 << 26) /* Bit 26: NBOOT0 option bit */
+#define FLASH_OPTR_NRST_MODE_SHIFT (27) /* Bits 27-28: PF2-NRST pin
configuration */
+#define FLASH_OPTR_NRST_MODE_MASK (0x3 << FLASH_OPTR_NRST_MODE_SHIFT)
+#define FLASH_OPTR_IRHEN (1 << 29) /* Bit 29: Internal reset
holder enable */
+#define FLASH_OPTR_FDCAN_BLCK_SHIFT (30) /* Bits 30-31: FDCAN bootloader
clock source */
+#define FLASH_OPTR_FDCAN_BLCK_MASK (0x3 << FLASH_OPTR_FDCAN_BLCK_SHIFT)
+
+/* Flash PCROP area A start address register (PCROP1ASR) */
+
+#define FLASH_PCROP1ASR_STRT_SHIFT (0)
+#define FLASH_PCROP1ASR_STRT_MASK (0x1ff <<
FLASH_PCROP1ASR_STRT_SHIFT)
+
+/* Flash PCROP area A end address register (PCROP1AER) */
+
+#define FLASH_PCROP1AER_PCROP1A_END_SHIFT (0)
+#define FLASH_PCROP1AER_PCROP1A_END_MASK (0x1ff <<
FLASH_PCROP1AER_PCROP1A_END_SHIFT)
+#define FLASH_PCROP1AER_PCROP_RDP (1 << 31)
+
+/* Flash WRP area A address register (WRP1AR) */
+
+#define FLASH_WRP1AR_WRP1A_STRT_SHIFT (0)
+#define FLASH_WRP1AR_WRP1A_STRT_MASK (0x7f <<
FLASH_WRP1AR_WRP1A_STRT_SHIFT)
+#define FLASH_WRP1AR_WRP1A_END_SHIFT (16)
+#define FLASH_WRP1AR_WRP1A_END_MASK (0x7f <<
FLASH_WRP1AR_WRP1A_END_SHIFT)
+
+/* Flash WRP area B address register (WRP1BR) */
+
+#define FLASH_WRP1BR_WRP1B_STRT_SHIFT (0)
+#define FLASH_WRP1BR_WRP1B_STRT_MASK (0x7f <<
FLASH_WRP1BR_WRP1B_STRT_SHIFT)
+#define FLASH_WRP1BR_WRP1B_END_SHIFT (16)
+#define FLASH_WRP1BR_WRP1B_END_MASK (0x7f <<
FLASH_WRP1BR_WRP1B_END_SHIFT)
+
+/* Flash PCROP area B start address register (PCROP1BSR) */
+
+#define FLASH_PCROP1BSR_PCROP1B_STRT_SHIFT (0)
+#define FLASH_PCROP1BSR_PCROP1B_STRT_MASK (0x1ff <<
FLASH_PCROP1BSR_PCROP1B_STRT_SHIFT)
+
+/* Flash PCROP area B end address register (PCROP1BER) */
+
+#define FLASH_PCROP1BER_PCROP1B_END_SHIFT (0)
+#define FLASH_PCROP1BER_PCROP1B_END_MASK (0x1ff <<
FLASH_PCROP1BER_PCROP1B_END_SHIFT)
+
+/* Flash Security register (SECR) */
+
+#define FLASH_SECR_SEC_SIZE_SHIFT (0) /* Bits 0-7: Securable
memory area size */
+#define FLASH_SECR_SEC_SIZE_MASK (0xff << FLASH_SECR_SEC_SIZE_SHIFT)
+ /* Bits 8-15: Reserved */
+#define FLASH_SECR_BOOT_LOCK (1 << 16) /* Bit 16: Used to force
boot from user area */
+ /* Bits 20-31: Reserved
*/
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H */
diff --git a/arch/arm/src/stm32f0l0g0/stm32_flash.c
b/arch/arm/src/stm32f0l0g0/stm32_flash.c
index cd3b6e2ace5..8e2d4b7dd59 100644
--- a/arch/arm/src/stm32f0l0g0/stm32_flash.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_flash.c
@@ -26,8 +26,8 @@
#include <nuttx/config.h>
-#if defined(CONFIG_STM32F0L0G0_STM32G0)
-# include "stm32g0_flash.c"
+#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0)
+# include "stm32g0c0_flash.c"
#else
# error "Flash driver unsupported on selected chip."
#endif
diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_flash.c
b/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c
similarity index 96%
rename from arch/arm/src/stm32f0l0g0/stm32g0_flash.c
rename to arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c
index e32010190dd..201619738e2 100644
--- a/arch/arm/src/stm32f0l0g0/stm32g0_flash.c
+++ b/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/stm32f0l0g0/stm32g0_flash.c
+ * arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -98,29 +98,35 @@
#endif
#if defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_4)
-# define FLASH_NBLOCKS 8
+# define FLASH_NBLOCKS 8
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_6)
-# define FLASH_NBLOCKS 16
+# define FLASH_NBLOCKS 16
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_8)
-# define FLASH_NBLOCKS 32
+# define FLASH_NBLOCKS 32
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_B)
-# define FLASH_NBLOCKS 64
+# define FLASH_NBLOCKS 64
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C)
-# define FLASH_NBLOCKS 128
-# define FLASH_DUAL_BANK 1
-# define FLASH_BANK2_BASE 0x08020000
+# define FLASH_NBLOCKS 128
+# ifdef CONFIG_ARCH_CHIP_STM32G0
+# define FLASH_DUAL_BANK 1
+# define FLASH_BANK2_BASE 0x08020000
+# endif
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E)
-# define FLASH_NBLOCKS 256
-# define FLASH_DUAL_BANK 1
-# define FLASH_BANK2_BASE 0x08040000
+# define FLASH_NBLOCKS 256
+# ifdef CONFIG_ARCH_CHIP_STM32G0
+# define FLASH_DUAL_BANK 1
+# define FLASH_BANK2_BASE 0x08040000
+# endif
#else
# error "Invalid flash configuration defined"
#endif
#ifdef FLASH_DUAL_BANK
# define FLASH_BANKSIZE (FLASH_NBLOCKS * FLASH_BLOCK_SIZE / 2)
+# define FLASH_SR_BSY (FLASH_SR_BSY1 | FLASH_SR_BSY2)
#else
# define FLASH_BANKSIZE (FLASH_NBLOCKS * FLASH_BLOCK_SIZE)
+# define FLASH_SR_BSY (FLASH_SR_BSY1)
#endif
/* Dual bank G0B1 MCUs have a non-linear mapping of block number between
@@ -301,8 +307,7 @@ static int flash_wait_for_operation(void)
for (i = 0; i < FLASH_TIMEOUT; i += 10)
{
- if (!(getreg32(STM32_FLASH_SR) &
- (FLASH_SR_CFGBSY | FLASH_SR_BSY1 | FLASH_SR_BSY2)))
+ if (!(getreg32(STM32_FLASH_SR) & (FLASH_SR_CFGBSY | FLASH_SR_BSY)))
{
timeout = false;
break;
@@ -852,7 +857,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf,
size_t count)
goto exit_with_unlock;
}
- /* Future improvements may add ECC checking here. */
+ /* Future improvements may add ECC checking here (STM32G0 only). */
}
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
@@ -877,7 +882,7 @@ exit_with_unlock:
break;
}
- /* Future improvements may add ECC checking here. */
+ /* Future improvements may add ECC checking here (STM32G0 only). */
}
modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_CLEAR_ERROR_FLAGS);
@@ -893,4 +898,4 @@ uint8_t up_progmem_erasestate(void)
return FLASH_ERASEDVALUE;
}
-#endif /* CONFIG_ARCH_HAVE_PROGMEM*/
\ No newline at end of file
+#endif /* CONFIG_ARCH_HAVE_PROGMEM */
