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from 3a878cacf63 boards/arm/rp23xx/pimoroni-pico-2-plus: Corrected all
defconfig files
new dcc9f257753 arch/risc-v/mpfs: Add a header file with E51 specific CSR
registers
new 480cd623d96 arch/risc-v/mpfs: Enable caches by default on E51 core
The 2 revisions listed above as "new" are entirely new to this
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Summary of changes:
arch/risc-v/src/mpfs/Kconfig | 6 ++++
arch/risc-v/src/mpfs/mpfs_e51_csr.h | 64 +++++++++++++++++++++++++++++++++++++
arch/risc-v/src/mpfs/mpfs_head.S | 16 ++++++++++
3 files changed, 86 insertions(+)
create mode 100644 arch/risc-v/src/mpfs/mpfs_e51_csr.h
