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commit fbd27c045bd51d87261286500d84165937c96c69 Author: Jukka Laitinen <[email protected]> AuthorDate: Wed Nov 19 11:44:57 2025 +0200 arch/imx9: Correct LPSPI TCR register PCS bit definitions According to the TRM, only bits 24-25 are reserved for chip select, and the maximum number of internal chip selects is 3 (on LPSPI4 bus only). Fix the TCR_PCS_MASK and remove extra definitions. Signed-off-by: Jukka Laitinen <[email protected]> --- arch/arm64/src/imx9/hardware/imx9_lpspi.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/src/imx9/hardware/imx9_lpspi.h b/arch/arm64/src/imx9/hardware/imx9_lpspi.h index 30361542653..6d7e7c233e1 100644 --- a/arch/arm64/src/imx9/hardware/imx9_lpspi.h +++ b/arch/arm64/src/imx9/hardware/imx9_lpspi.h @@ -284,16 +284,11 @@ #define LPSPI_TCR_BYSW (1 << 22) /* Bit 22: Byte Swap (BYSW) */ #define LPSPI_TCR_LSBF (1 << 23) /* Bit 23: LSB First (LSBF) */ # define LPSPI_TCR_MSBF (0 << 23) /* MSB First */ -#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-26: Peripheral Chip Select (PCS) */ -#define LPSPI_TCR_PCS_MASK (0x07 << LPSPI_TCR_PCS_SHIFT) +#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-25: Peripheral Chip Select (PCS) */ +#define LPSPI_TCR_PCS_MASK (0x03 << LPSPI_TCR_PCS_SHIFT) # define LPSPI_TCR_PCS_0 (0x00 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[0] */ # define LPSPI_TCR_PCS_1 (0x01 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[1] */ # define LPSPI_TCR_PCS_2 (0x02 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[2] */ -# define LPSPI_TCR_PCS_3 (0x03 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[3] */ -# define LPSPI_TCR_PCS_4 (0x04 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[4] */ -# define LPSPI_TCR_PCS_5 (0x05 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[5] */ -# define LPSPI_TCR_PCS_6 (0x06 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[6] */ -# define LPSPI_TCR_PCS_7 (0x07 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[7] */ #define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value (PRESCALE) */ #define LPSPI_TCR_PRESCALE_MASK (0x07 << LPSPI_TCR_PRESCALE_SHIFT)
