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new d98e7a7b68d risc-v/litex: For vexriscv, point docs at linux CPU
variant instead of secure.
d98e7a7b68d is described below
commit d98e7a7b68da4585c79514de5abc769b67b19633
Author: Justin Erenkrantz <[email protected]>
AuthorDate: Fri Dec 12 10:32:53 2025 -0500
risc-v/litex: For vexriscv, point docs at linux CPU variant instead of
secure.
The secure CPU variant of vexriscv immediately panics after bring up.
However, the linux CPU variant of the vexriscv core does work successfully.
Signed-off-by: Justin Erenkrantz <[email protected]>
---
Documentation/platforms/risc-v/litex/boards/arty_a7/README.txt | 2 +-
Documentation/platforms/risc-v/litex/boards/arty_a7/index.rst | 2 +-
Documentation/platforms/risc-v/litex/cores/vexriscv/index.rst | 9 +++++++++
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/platforms/risc-v/litex/boards/arty_a7/README.txt
b/Documentation/platforms/risc-v/litex/boards/arty_a7/README.txt
index 773169569f6..a90a3f88b95 100644
--- a/Documentation/platforms/risc-v/litex/boards/arty_a7/README.txt
+++ b/Documentation/platforms/risc-v/litex/boards/arty_a7/README.txt
@@ -6,7 +6,7 @@
and flash to arty_a7 board
$ cd litex-boards/litex_boards/targets
- $ ./digilent_arty.py --with-ethernet --with-sdcard --uart-baudrate 1000000
--cpu-type=vexriscv --cpu-variant=secure --build --load --flash
+ $ ./digilent_arty.py --with-ethernet --with-sdcard --uart-baudrate 1000000
--cpu-type=vexriscv --cpu-variant=linux --build --load --flash
3. Configure and build NuttX
diff --git a/Documentation/platforms/risc-v/litex/boards/arty_a7/index.rst
b/Documentation/platforms/risc-v/litex/boards/arty_a7/index.rst
index 421fa608623..3de222cdbf9 100644
--- a/Documentation/platforms/risc-v/litex/boards/arty_a7/index.rst
+++ b/Documentation/platforms/risc-v/litex/boards/arty_a7/index.rst
@@ -72,7 +72,7 @@ Flashing
.. code:: console
$ cd litex-boards/litex_boards/targets
- $ ./digilent_arty.py --with-ethernet --with-sdcard --uart-baudrate 1000000
--cpu-type=vexriscv --cpu-variant=secure --build --load --flash
+ $ ./digilent_arty.py --with-ethernet --with-sdcard --uart-baudrate 1000000
--cpu-type=vexriscv --cpu-variant=linux --build --load --flash
2. Next, set up a TFTP server on your host machine, copy ``nuttx.bin`` to your
diff --git a/Documentation/platforms/risc-v/litex/cores/vexriscv/index.rst
b/Documentation/platforms/risc-v/litex/cores/vexriscv/index.rst
index 6b39c841c8b..5e2afe46226 100644
--- a/Documentation/platforms/risc-v/litex/cores/vexriscv/index.rst
+++ b/Documentation/platforms/risc-v/litex/cores/vexriscv/index.rst
@@ -4,6 +4,15 @@ Vexriscv Core
The vexriscv core only supports standard "Flat builds", consisting of a single
binary.
+Configuration
+-------------
+
+For vexriscv, the linux CPU variant is required. Please consult the
appropriate board
+documentation for flashing gateware.
+
+If you use the secure CPU variant, you may encounter a kernel panic on startup
- please see
+https://github.com/apache/nuttx/pull/17494 for an example.
+
Building
--------
