hujun260 opened a new pull request, #17955:
URL: https://github.com/apache/nuttx/pull/17955
## Summary
This PR optimizes the address environment synchronization mechanism by
replacing
global critical section locks with a lightweight spinlock. This reduces
interrupt
latency and improves concurrency on multi-core systems. Additionally, the
reference
counter is converted to atomic operations for better thread safety.
## Changes
The optimization involves three key changes:
1. **include/nuttx/addrenv.h** - Replace int with atomic_t:
- Add `#include <nuttx/atomic.h>` for atomic operations
- Change `refs` field in `struct addrenv_s` from `int` to `atomic_t`
- Enables lock-free reference counting operations
- Improves thread safety without critical sections
2. **sched/addrenv/addrenv.c** - Replace critical section with spinlock:
- Add static spinlock: `static spinlock_t g_addrenv_lock = SP_UNLOCKED`
- Replace `enter_critical_section()` with
`spin_lock_irqsave(&g_addrenv_lock)`
- Replace `leave_critical_section()` with
`spin_unlock_irqrestore(&g_addrenv_lock, flags)`
- More targeted synchronization reduces system-wide interrupt latency
- Update reference counter initialization: `atomic_set(&addrenv->refs, 1)`
## Benefits
- **Performance**: Reduces interrupt latency by using spinlock instead of
global critical section
- **Scalability**: Better concurrency on SMP systems with per-subsystem
spinlock
- **Atomicity**: Thread-safe reference counting without blocking
- **Efficiency**: Lighter weight synchronization primitive for this specific
use case
## Technical Details
**Why spinlock instead of critical section?**
- Critical section disables interrupts globally on all CPUs
- Spinlock is localized to the addrenv subsystem
- Reduces latency for unrelated interrupt handlers
**Why atomic_t for refs?**
- Atomic operations don't require locks
- Thread-safe on all architectures
- Better performance for simple counters
## Testing
Tested on:
- **Platform**: NuttX SMP systems (multi-core ARM)
- **Configuration**: CONFIG_SMP enabled with address environment support
- **Test scenarios**:
- Concurrent address environment switches
- Task creation/destruction with different memory layouts
- Signal handling during address environment operations
- Interrupt latency measurements
- Memory pressure scenarios with multiple tasks
- **Result**:
- Reduced interrupt latency in addrenv operations
- Correct reference counting and memory cleanup
- No deadlocks or race conditions
- Improved system responsiveness
## Impact
- **Performance**: Reduced interrupt latency and improved concurrency
- **Stability**: Maintains correct semantics with simpler synchronization
- **Compatibility**: No API changes; internal optimization only
- **Code Quality**: Cleaner synchronization model with atomic operations
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