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commit 01e5e50619f53158f7d12a3f0eb2866944306c40 Author: ouyangxiangzhen <[email protected]> AuthorDate: Thu Jul 24 20:31:32 2025 +0800 testing/time: Relax the timing constraints. On SIM and QEMU, it is inevitable that the simulating vCPU got preempted by other threads, causing large timing delay. This commit relax the timing constraints to reduce the CT error. Signed-off-by: ouyangxiangzhen <[email protected]> --- testing/testsuites/kernel/time/cases/clock_test_timer03.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testing/testsuites/kernel/time/cases/clock_test_timer03.c b/testing/testsuites/kernel/time/cases/clock_test_timer03.c index 7539f4479..76a42c760 100644 --- a/testing/testsuites/kernel/time/cases/clock_test_timer03.c +++ b/testing/testsuites/kernel/time/cases/clock_test_timer03.c @@ -123,7 +123,7 @@ void test_nuttx_clock_test_timer03(FAR void **state) start.tv_sec * (int64_t)(1e9) - start.tv_nsec; failed += (escaped < expected || - (escaped - expected) >= 20000000); /* 20000000, 2 ticks. */ + (escaped - expected) > 100000000ul); /* 100 ms */ syslog(LOG_INFO, "expected = %" PRId64 " escaped = %" PRId64 "failed = %d", expected, escaped, failed); }
