jlaitine opened a new pull request, #18403: URL: https://github.com/apache/nuttx/pull/18403
## Summary This PR fixes the following issues for the NXP93/NXP95 uSDHC driver: - The macros CONFIG_IMX9_USDHC_DMA and CONFIG_ARM64_DCACHE_DISABLE were mixed up a bit. All combinations of these macros should compile and work. - Some sdcards don't work with current board setups. The boards currently configure the cards to 50MHz, but this is really only supported if the card is set to either "high speed mode" at 3.3V, or some SDR25 or higher 1.8V. This PR sets the SD card to high speed mode if the configured speed is above 25 MHz. - The bus speed configuration for boards is confusing, the boards directly define the prescalers and dividers, but root clocks are hidden in the driver. This PR allows configuring the wanted bus speed directly, and dividers are calculated by the driver - The root clock of the usdhc block is unnecesary low, but implementing the above allows easily increasing that. ## Impact This impacts imx9 architecture boards using SD cards / uSDHC driver, fixing stability issues ## Testing This is tested on i.MX93 EVK and with a custom i.MX93 board and with several SD cards (SanDisk, Kingston). Specifically "SanDisk 8GB Industrial XI" card is tested at most, since this card failed constantly when wrongly used with 50MHz bus without switching to high speed. The tests include: 1. Measured the freuencies with oscilloscope - Initialization frequency 400kHZ - 1-bit frequency 25 MHz - 4-bit high-speed frequency 50 MHz Here is one image, showing the 50MHz operation after card has been switched to HS mode. The red arrow shows the place where SOC writes to the card (data changes exactly at the falling edge). The blue arrow shows card writing to SoC, the data is set by the card 6ns after the clock rising edge. Before switch the data is set 6ns after the clock falling edge -> confirming that the switch was done successfully by the card. <img width="1920" height="1061" alt="ft_sdcard_1" src="https://github.com/user-attachments/assets/41efe4ed-9174-432f-a227-0fcd6fb8c6b0"; /> 2. Checked file system operation (there are much more real life testing with reading & writing, but this sanity check was done with also all the cache&dma combinations) ``` nsh> mount -t vfat /dev/mmcsd0 /fs/microsd nsh> cd /fs/microsd nsh> ls /fs/microsd: test.txt nsh> echo "Hello World!" > test.txt nsh> cat test.txt Hello World! ``` 3. Added debug code to dump the CMD6 response after the succesful HS switch (code uses bytes 12,13 and 16 acc. to the "SD Specifications Part 1 Physical Layer Simplified Specification" ``` imx9_sdcard_hs_mode: 00 c8 80 01 imx9_sdcard_hs_mode: 80 01 80 01 imx9_sdcard_hs_mode: 80 01 c0 01 imx9_sdcard_hs_mode: 80 03 00 00 imx9_sdcard_hs_mode: 01 00 00 00 imx9_sdcard_hs_mode: 00 00 00 00 imx9_sdcard_hs_mode: 00 00 00 00 imx9_sdcard_hs_mode: 00 00 00 00 imx9_sdcard_hs_mode: 00 00 00 00 imx9_sdcard_hs_mode: 00 00 00 00 imx9_sdcard_hs_mode: 00 00 00 00 imx9_sdcard_hs_mode: 00 00 00 00 imx9_sdcard_hs_mode: 00 00 00 00 imx9_sdcard_hs_mode: 00 00 00 00 imx9_sdcard_hs_mode: 00 00 00 00 imx9_sdcard_hs_mode: 00 00 00 00 ``` 4. With a real application (px4, logger), wrote larger files (several MB each) to the card, and reading them back on PC and verifying the content. i.MX95 is not tested (I don't have the EVK), but this is essentially the same SoC regarding the uSD and clocking. It only has more cpu cores. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
