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commit a8495b118c0b83c27e99998858a74232398ca9c2 Author: Tiago Medicci Serrano <[email protected]> AuthorDate: Fri Mar 6 09:11:52 2026 -0300 Documentation: Add documentation for ESP32-P4 and Function-EV-Board This commit adds documentation entries for ESP32-P4 chip and its board (ESP32-P4 Function-EV-Board). Signed-off-by: Tiago Medicci Serrano <[email protected]> --- ...esp32-p4-function-ev-board-isometric_v1.5.2.png | Bin 0 -> 494986 bytes .../boards/esp32p4-function-ev-board/index.rst | 321 ++++++++++++++++++++ Documentation/platforms/risc-v/esp32p4/index.rst | 330 +++++++++++++++++++++ 3 files changed, 651 insertions(+) diff --git a/Documentation/platforms/risc-v/esp32p4/boards/esp32p4-function-ev-board/esp32-p4-function-ev-board-isometric_v1.5.2.png b/Documentation/platforms/risc-v/esp32p4/boards/esp32p4-function-ev-board/esp32-p4-function-ev-board-isometric_v1.5.2.png new file mode 100644 index 00000000000..601895eef52 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32p4/boards/esp32p4-function-ev-board/esp32-p4-function-ev-board-isometric_v1.5.2.png differ diff --git a/Documentation/platforms/risc-v/esp32p4/boards/esp32p4-function-ev-board/index.rst b/Documentation/platforms/risc-v/esp32p4/boards/esp32p4-function-ev-board/index.rst new file mode 100644 index 00000000000..0a3b0555a47 --- /dev/null +++ b/Documentation/platforms/risc-v/esp32p4/boards/esp32p4-function-ev-board/index.rst @@ -0,0 +1,321 @@ +========================== +ESP32-P4-Function-EV-Board +========================== + +.. tags:: chip:esp32p4, arch:risc-v, vendor:espressif + +.. figure:: esp32-p4-function-ev-board-isometric_v1.5.2.png + :align: center + :alt: ESP32-P4-Function-EV-Board v1.5.2 + + ESP32-P4-Function-EV-Board v1.5.2 + +ESP32-P4-Function-EV-Board is a multimedia development board based on the +ESP32-P4 chip. The board pairs ESP32-P4 with external peripherals that showcase +its rich feature set, such as USB 2.0, MIPI-CSI/DSI, an H.264 encoder, audio +codec, and a 7-inch capacitive touch LCD with a resolution of 1024 x 600. + +Additionally, the board integrates a 2.4 GHz Wi‑Fi 6 and Bluetooth LE module +(``ESP32-C6-MINI-1``) for wireless connectivity. Most I/O pins are broken out to +pin headers for easy interfacing, allowing rapid prototyping for applications such +as smart displays, network cameras, and audio devices. + +The board is available in two hardware revisions: + +* **v1.5.2** (current): replaces the external CP2102N USB-to-UART bridge with + the ESP32-P4's built-in USB Serial/JTAG interface, and adds a dedicated + USB Full-speed port. This is the recommended revision for new designs. +* **v1.4** (legacy): uses a CP2102N USB-to-UART bridge chip connected to + UART0 (GPIO37/GPIO38) for flashing and serial debugging. + +For full board details refer to the official user guides: + +* `ESP32-P4-Function-EV-Board v1.5.2 User Guide <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32p4/esp32-p4-function-ev-board/user_guide.html>`_ (current) +* `ESP32-P4-Function-EV-Board v1.4 User Guide <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32p4/esp32-p4-function-ev-board/user_guide_v1.4.html>`_ (legacy) + +Features +======== + +* Based on ESP32-P4 SoC (RISC-V), featuring powerful image and voice processing +* In-package PSRAM (16 MB or 32 MB depending on chip variant) +* Rich multimedia I/O: USB 2.0, MIPI-CSI/DSI, H.264 encoder +* 7" 1024x600 capacitive touch LCD (via adapter board) +* On-board audio path: ES8311 codec + NS4150B audio power amplifier +* On-board microphone and speaker connector (up to 3 W into 4 Ω) +* Expansion header with the majority of GPIOs broken out (header ``J1``) +* External wireless module: ``ESP32-C6-MINI-1`` providing Wi‑Fi 6 and BLE +* Multiple USB-C ports: USB 2.0 OTG High-Speed, USB Full-speed (v1.5.2) or + USB Power-in (v1.4), and USB Serial/JTAG (v1.5.2) or USB-to-UART via + CP2102N (v1.4) for flashing and debug + +.. note:: + Wireless connectivity is provided by the on-board ``ESP32-C6-MINI-1`` module. + The ESP32-P4 itself does not integrate Wi‑Fi/BLE radios. + +Buttons and LEDs +================ + +Board Buttons +------------- + +* ``BOOT`` button: controls boot mode on reset; available for software input after boot. +* ``RST`` button: resets the board (chip enable / reset line), not software-controlled. + +Board LEDs +---------- + +* A power indicator LED may be present depending on hardware revision. +* No dedicated user-programmable LED is provided on the core board; LCD backlight is PWM-controlled instead (see below). + +Display and Camera +================== + +The LCD adapter connects to the ESP32-P4 MIPI DSI connector (J3 on adapter). +Default control pins on the EV board are: + +* ``GPIO27``: LCD Reset (``RST_LCD``) +* ``GPIO26``: LCD Backlight PWM (``PWM``) + +Connection summary (refer to the user guide for images and full directions): + +* LCD adapter ``J3`` header → EV-Board MIPI DSI connector (ribbon cable in reverse direction) +* LCD adapter ``RST_LCD`` (``J6``) → ``GPIO27`` (header ``J1``) +* LCD adapter ``PWM`` (``J6``) → ``GPIO26`` (header ``J1``) +* LCD adapter power: via its USB on ``J1`` or by wiring 5V/GND from the EV-Board + +The camera adapter connects to the MIPI CSI connector (ribbon cable in forward direction). + +Pin Mapping +=========== + +Most ESP32-P4 GPIOs are exposed on the header block ``J1``. The EV-Board user +guide documents the full pinout and header numbering; see the "Header Block" +tables in the user guide for details. Selected defaults used on this board: + +===== =========================== ============================================ +Pin Signal/Function Notes +===== =========================== ============================================ +26 PWM (LCD backlight) Default backlight control +27 RST_LCD (LCD reset) Default LCD reset control +37 U0TXD Default UART0 TX exposed on header +38 U0RXD Default UART0 RX exposed on header +===== =========================== ============================================ + +Power Supply +============ + +The board can be powered via any of the USB Type‑C ports. The available ports +differ by hardware revision: + +* **v1.5.2**: USB 2.0 Type-C Port (OTG High-Speed), USB Full-speed Port, or + USB Serial/JTAG Port. +* **v1.4**: USB 2.0 Type-C Port (OTG High-Speed), USB Power-in Port, or + USB-to-UART Port (CP2102N bridge). + +If the debug cable cannot provide enough current, use a separate power adapter +connected to any available USB‑C port. + +Installation +============ + +Follow the ESP32-P4 chip documentation for toolchain setup and required tools +(:doc:`/platforms/risc-v/esp32p4/index`). In summary: + +* Install a RISC‑V GCC toolchain (e.g., xPack riscv-none-elf-gcc) +* Install ``esptool.py`` (``pipx install esptool`` recommended or use a venv) +* Optionally, set up ``openocd-esp32`` for JTAG debugging + +Building NuttX +============== + +All configurations can be selected using the board identifier with the NuttX build +tools. The basic shell configuration: + +.. code-block:: console + + $ ./tools/configure.sh esp32p4-function-ev-board:nsh + $ make -j$(nproc) + +Flashing +======== + +Use the standard flashing flow. Replace ``<port>`` with the serial device exposed +by the board: + +* **v1.5.2**: the USB Serial/JTAG port creates a CDC ACM device, typically + ``/dev/ttyACM0``. Please note that most of the configs use UART0 (GPIO37/GPIO38) + as the serial console (except for `usbconsole`). For UART0-based terminal, an external + USB-to-UART bridge is required to be attached to UART0 port (GPIO37/GPIO38) pins and the + board requires to be manually set to download mode by pressing the BOOT button and then + the RST button (releasing the RST before the BOOT button). +* **v1.4**: the on-board CP2102N USB-to-UART bridge creates a USB-serial device, typically + ``/dev/ttyUSB0``. + + +Connect the appropriate USB‑C port and run: + +.. code-block:: console + + $ make -j$(nproc) flash ESPTOOL_PORT=<port> ESPTOOL_BINDIR=./ + +After flashing, connect a serial console at 115200 8N1 to interact with NSH. + +Configurations +============== + +All of the configurations presented below can be tested by running the following commands:: + + $ ./tools/configure.sh esp32p4-function-ev-board:<config_name> + $ make -j + +Where ``<config_name>`` is one of the names listed below (e.g., ``nsh``, ``adc``). +Then use a serial console terminal like ``picocom`` configured to 115200 8N1. + +adc +--- + +Enables the ADC driver. ADC unit(s) are registered (``/dev/adc0`` as ADC1). +Attenuation, mode, and channel set can be adjusted in ``ADC Configuration``. + +bmp180 +------ + +Enables the BMP180 pressure sensor over I2C. Use the ``bmp180`` app to read samples. + +buttons +------- + +Demonstrates the buttons subsystem. Run ``buttons`` and press the board's BOOT button +to see samples appearing. + +capture +------- + +Enables the capture driver and the capture example to measure duty cycle/frequency +of an external signal. + +crypto +------ + +Enables cryptographic hardware support for SHA algorithms and a ``/dev/crypto`` node. + +efuse +----- + +Enables the eFuse driver (supports virtual eFuses). Access via ``/dev/efuse``. + +gpio +---- + +Tests the GPIO driver. Provides examples for output control and edge-triggered interrupts. + +i2c +--- + +Enables I2C utilities. ``i2c dev 0x00 0x7f`` can scan the bus. + +i2schar +------- + +Enables the I2S character device and ``i2schar`` example for TX/RX testing over I2S0. + +motor +----- + +Enables the MCPWM peripheral for brushed DC motor control (``/dev/motor0``). + +nsh +--- + +Basic configuration to run the NuttShell (NSH). + +ostest +------ + +Runs OS tests from ``apps/testing/ostest``. + +pwm +--- + +Demonstrates PWM via LEDC. The ``pwm`` app toggles output with default frequency/duty. + +qencoder +-------- + +Enables Quadrature Encoder support via PCNT. The ``qe`` sample reads pulses on the configured pins. + +random +------ + +Demonstrates the hardware RNG. + +rmt +--- + +Configures an RMT TX/RX pair and the ``rmtchar`` example. Also includes ``ws2812`` for addressable LEDs. + +rtc +--- + +Demonstrates RTC alarms via the ``alarm`` app. + +sdm +--- + +Enables Sigma-Delta Modulation (SDM) driver for LED dimming/simple DAC; see ``dac`` test. + +spi +--- + +Enables SPI master driver. Loop MOSI↔MISO and run ``spi exch -b 2 "AB"`` to verify. + +spiflash +-------- + +Tests the external SPI flash via SPI1. Defaults to SmartFS; see ``mksmartfs``/``mount`` instructions. + +spislv +------ + +Enables SPI2 Slave mode for testing host-to-device transactions. + +temperature_sensor +------------------ + +Enables the internal temperature sensor and related character device/uORB options. + +tickless +-------- + +Enables tickless scheduling for reduced idle power. + +timers +------ + +Demonstrates general-purpose timers via the ``timer`` example. + +twai +---- + +Enables the Two-Wire Automotive Interface (CAN/TWAI). Loopback testing is available via Kconfig. + +usbconsole +---------- + +Tests the USB Serial/JTAG console. On v1.5.2 this uses the ESP32-P4's built-in +USB Serial/JTAG peripheral exposed on the dedicated USB Serial/JTAG port +(``/dev/ttyACM0``). +On v1.4, an external cable is required to be attached to USB Serial/JTAG port (GPIO24/GPIO25). + +watchdog +-------- + +Demonstrates MWDT/RWDT watchdog timers via the ``wdog`` app. + +Related Documentation +===================== + +* User Guide (current): `ESP32-P4-Function-EV-Board v1.5.2 <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32p4/esp32-p4-function-ev-board/user_guide.html>`_ +* User Guide (legacy): `ESP32-P4-Function-EV-Board v1.4 <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32p4/esp32-p4-function-ev-board/user_guide_v1.4.html>`_ +* ESP32-P4 Product Overview: `ESP32-P4 Product Overview <https://docs.espressif.com/projects/esp-hardware-design-guidelines/en/latest/esp32p4/product-overview.html>`_ +* ESP32-P4 TRM: `ESP32-P4 Technical Reference Manual (v1.3) <https://documentation.espressif.com/esp32-p4-chip-revision-v1.3_technical_reference_manual_en.pdf>`_ diff --git a/Documentation/platforms/risc-v/esp32p4/index.rst b/Documentation/platforms/risc-v/esp32p4/index.rst new file mode 100644 index 00000000000..f8bac1e7439 --- /dev/null +++ b/Documentation/platforms/risc-v/esp32p4/index.rst @@ -0,0 +1,330 @@ +================== +Espressif ESP32-P4 +================== + +.. tags:: chip:esp32p4, arch:risc-v, vendor:espressif + +The ESP32-P4 is a high-performance, highly integrated SoC featuring RISC-V +processors, rich multimedia capabilities, and abundant peripherals. It targets +applications that demand efficient power usage, compact design, security, high +performance, and reliability. + +Key highlights include: + +* RISC-V 32-bit processors + * Dual-core High Performance (HP) running at 360 MHz + * Low Power core (LP) at 40 MHz +* Powerful image and voice processing capability +* In-package PSRAM (16 MB or 32 MB depending on the chip variant) +* 55 GPIOs and rich peripheral set +* Additional multimedia and I/O features commonly used on ESP32-P4 based designs, such as USB 2.0, MIPI-CSI/DSI, and H.264 encoder + +Typical application scenarios include smart home, industrial automation, audio devices, +IoT sensor hubs, data loggers, video streaming cameras, USB devices, and speech/image +recognition systems. + +References: see the ESP Hardware Design Guidelines for ESP32-P4 and the Technical +Reference Manual for detailed SoC architecture, memory map, and peripheral +descriptions. + +* Product overview: `ESP32-P4 Product Overview <https://docs.espressif.com/projects/esp-hardware-design-guidelines/en/latest/esp32p4/product-overview.html>`_ +* Datasheet: `ESP32-P4 Datasheet (v1.3) <https://documentation.espressif.com/esp32-p4-chip-revision-v1.3_datasheet_en.pdf>`_ +* Technical Reference Manual: `ESP32-P4 TRM (v1.3) <https://documentation.espressif.com/esp32-p4-chip-revision-v1.3_technical_reference_manual_en.pdf>`_ + +ESP32-P4 Toolchain +================== + +A generic RISC-V toolchain can be used to build ESP32-P4 projects. It's recommended +to use the same toolchain version used by NuttX CI for RISC-V. +Please refer to the Docker +`container <https://github.com/apache/nuttx/tree/master/tools/ci/docker/linux/Dockerfile>`_ +and check for the current compiler version being used. For instance: + +.. code-block:: + + ############################################################################### + # Build image for tool required by RISCV builds + ############################################################################### + FROM nuttx-toolchain-base AS nuttx-toolchain-riscv + # Download the latest RISCV GCC toolchain prebuilt by xPack + RUN mkdir -p riscv-none-elf-gcc && \ + curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v14.2.0-3/xpack-riscv-none-elf-gcc-14.2.0-3-linux-x64.tar.gz"; \ + | tar -C riscv-none-elf-gcc --strip-components 1 -xz + +Installing +---------- + +First, create a directory to hold the toolchain: + +.. code-block:: console + + $ mkdir -p /path/to/your/toolchain/riscv-none-elf-gcc + +Download and extract the recommended toolchain (example uses xPack GCC): + +.. code-block:: console + + $ curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v14.2.0-3/xpack-riscv-none-elf-gcc-14.2.0-3-linux-x64.tar.gz"; \ + | tar -C /path/to/your/toolchain/riscv-none-elf-gcc --strip-components 1 -xz + +Add the toolchain to your ``PATH``: + +.. code-block:: console + + $ echo "export PATH=/path/to/your/toolchain/riscv-none-elf-gcc/bin:$PATH" >> ~/.bashrc + +You can edit your shell's rc files if you don't use bash. + +Building and flashing NuttX +=========================== + +Installing esptool +------------------ + +First, make sure that ``esptool.py`` is installed and up-to-date. +This tool is used to convert the ELF to an ESP image and to flash the image into the board. + +It can be installed with: ``pip install esptool``. + +.. warning:: + Installing ``esptool.py`` may require a Python virtual environment on newer systems. + If the ``pip install`` command is blocked by an externally-managed environment policy, + consider using a virtual environment (``python3 -m venv``) or a tool like ``pipx``. + +Bootloader and partitions +------------------------- + +NuttX supports booting ESP SoCs directly using "Simple Boot". Depending on future +requirements, an externally-built 2nd stage bootloader (e.g., MCUboot) may also be +used. Refer to board-specific documentation for the selected boot method and +partitioning. + +Building and Flashing +--------------------- + +Building and flashing are board-specific. Once an ESP32-P4 board is selected via +``./tools/configure.sh``, in general you can build and flash with: + +.. code-block:: console + + $ make -j$(nproc) + $ make -j$(nproc) flash ESPTOOL_PORT=<port> ESPTOOL_BINDIR=./ + +Where ``<port>`` is the serial/USB port connected to your board. + +Please check `Supported Boards`_ for the actual commands. + +Debugging +========= + +Debugging with ``openocd`` and ``gdb`` +-------------------------------------- + +Espressif uses a specific version of OpenOCD to support ESP chips: ``openocd-esp32``. +Please check `Building OpenOCD from Sources <https://docs.espressif.com/projects/esp-idf/en/stable/api-guides/jtag-debugging/index.html#jtag-debugging-building-openocd>`_ +for more information on how to build OpenOCD. + +ESP32-P4 integrates a USB-to-JTAG adapter, so no external JTAG adapter is necessary. + +OpenOCD can then be used:: + + openocd -s <tcl_scripts_path> -c 'set ESP_RTOS hwthread; set ESP_ONLYCPU 1' -f board/esp32p4-builtin.cfg -c 'init; reset halt; esp appimage_offset 0x2000' + +.. note:: + - ``appimage_offset`` should be set to ``0x2000`` when ``Simple Boot`` is used. + - ``-s <tcl_scripts_path>`` defines the path to the OpenOCD scripts. Usually set to `tcl` if running openocd from its source directory. + It can be omitted if `openocd-esp32` was installed in the system with `sudo make install`. + +Once OpenOCD is running, GDB can be used to connect to the device and debug the running application:: + + riscv-none-elf-gdb -x gdbinit nuttx + +whereas the content of the ``gdbinit`` file is:: + + target remote :3333 + set remote hardware-watchpoint-limit 2 + mon reset halt + flushregs + monitor reset halt + thb nsh_main + c + +.. note:: ``nuttx`` is the ELF file generated by the build process. Please note that ``CONFIG_DEBUG_SYMBOLS`` must be enabled in the ``menuconfig``. + +Please refer to :doc:`/quickstart/debugging` for more information about debugging techniques. + +Stack Dump and Backtrace Dump +----------------------------- + +NuttX can dump the stack of a task and produce backtraces to aid debugging, +especially when diagnosing exceptions and crashes. + +Enable the following options to use this feature: ``CONFIG_SCHED_BACKTRACE`` +and ``CONFIG_DEBUG_SYMBOLS``; optionally enable ``CONFIG_ALLSYMS`` to have +symbolized backtraces at runtime (at the expense of larger binary size). + +When ``CONFIG_ALLSYMS`` is not enabled, use NuttX's ``./tools/btdecode.sh`` tool to +translate addresses into symbols by providing the captured console log and the +ELF file. + +Example - Crash Dump +^^^^^^^^^^^^^^^^^^^^ + +A typical crash dump, caused by an illegal load with ``CONFIG_SCHED_BACKTRACE`` and +``CONFIG_DEBUG_SYMBOLS`` enabled, is shown below:: + + riscv_exception: EXCEPTION: Store/AMO access fault. MCAUSE: 00000007, EPC: 40017174, MTVAL: 00000000 + riscv_exception: PANIC!!! Exception = 00000007 + dump_assert_info: Current Version: NuttX 10.4.0 baf7d9dd3b-dirty Oct 24 2025 15:54:40 risc-v + dump_assert_info: Assertion failed panic: at file: common/riscv_exception.c:134 task: backtrace process: backtrace 0x4001712e + up_dump_register: EPC: 40017174 + up_dump_register: A0: 0000005a A1: 00000000 A2: 00000002 A3: 00000004 + up_dump_register: A4: 7ffffffe A5: 00000000 A6: 7fffffff A7: 00000000 + up_dump_register: T0: 4fc1a058 T1: 0000000f T2: ffffffff T3: 00000000 + up_dump_register: T4: 00000000 T5: 00000000 T6: 00000000 + up_dump_register: S0: 4ff0a776 S1: 4ff0a760 S2: 00000000 S3: 00000000 + up_dump_register: S4: 00000000 S5: 00000000 S6: 00000000 S7: 00000000 + up_dump_register: S8: 00000000 S9: 00000000 S10: 00000000 S11: 00000000 + up_dump_register: SP: 4ff0b710 FP: 4ff0a776 TP: 00000000 RA: 40017174 + dump_stackinfo: User Stack: + dump_stackinfo: base: 0x4ff0a780 + dump_stackinfo: size: 00004048 + dump_stackinfo: sp: 0x4ff0b710 + stack_dump: 0x4ff0b6f0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001880 + stack_dump: 0x4ff0b710: 00000000 4ff0a3b0 4001712e 400098f8 00000000 00000000 00000002 4ff0a760 + stack_dump: 0x4ff0b730: 00000000 00000000 00000000 400070c4 00000000 00000000 00000000 00000000 + stack_dump: 0x4ff0b750: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + sched_dumpstack: backtrace| 2: 0x40017174 + dump_tasks: PID GROUP PRI POLICY TYPE NPX STATE EVENT SIGMASK STACKBASE STACKSIZE COMMAND + dump_tasks: ---- --- --- -------- ------- --- ------- ---------- ---------------- 0x4ff066c0 2048 irq + dump_task: 0 0 0 FIFO Kthread - Ready 0000000000000000 0x4ff08984 2032 Idle_Task + dump_task: 1 1 100 RR Task - Waiting Semaphore 0000000000000000 0x4ff09898 1992 nsh_main + dump_task: 2 2 255 RR Task - Running 0000000000000000 0x4ff0a780 4048 backtrace task + sched_dumpstack: backtrace| 0: 0x4000bb20 + sched_dumpstack: backtrace| 1: 0x4000c088 + sched_dumpstack: backtrace| 2: 0x40017174 + +The lines starting with ``sched_dumpstack`` show the backtrace of the tasks. By checking it, it is +possible to track the root cause of the crash. Saving this output to a file and using the ``btdecode.sh``:: + + ./tools/btdecode.sh esp32p4 backtrace.log + Backtrace for task 2: + 0x40017174: assert_on_task at backtrace_main.c:168 + (inlined by) backtrace_main at backtrace_main.c:204 + + Backtrace dump for all tasks: + + Backtrace for task 2: + 0x40017174: assert_on_task at backtrace_main.c:168 + (inlined by) backtrace_main at backtrace_main.c:204 + + Backtrace for task 1: + 0x4000c088: sys_call0 at syscall.h:161 + (inlined by) up_switch_context at riscv_switchcontext.c:83 + + Backtrace for task 0: + 0x4000bb20: up_idle at esp_idle.c:76 + +Peripheral Support +================== + +The following list indicates the state of peripherals' support in NuttX on +ESP32-P4 based on current Kconfig options and upstream support status. Refer to +board documentation for what is enabled by default. + +HP Peripherals +-------------- + +================= ======= ================================== +Peripheral Support NOTES +================= ======= ================================== +SPI Yes SPI2 master/slave; bitbang +I2C Yes +I2S Yes +ADC Yes +ISP No +PPA No +GPIO Yes Dedicated GPIO supported +UART Yes +Bit Scrambler No +SD/MMC Host No +H264 Encoder No +2D-DMA No +TWAI (CAN) Yes TWAI0/1 +Pulse Counter Yes Implemented as Quadrature Encoder +RMT Yes +USB Serial/JTAG Yes +JPEG Codec No +I3C No +GDMA Yes +SOC ETM No +USB 2.0 OTG No +Camera Interface No +MIPI CSI No +LED PWM Yes +MCPWM Yes Motor control and capture +Parallel IO No +LCD Interface No +MIPI DSI No +Timers Yes +Watchdog Yes MWDT0/1 and RWDT +Ethernet No +Brownout No +Debug Probe No +================= ======= ================================== + +LP Peripherals +-------------- + +================= ======= ================================== +Peripheral Support NOTES +================= ======= ================================== +LP SPI No +LP I2C No +LP I2S No +LP UART No +LP GPIO No +LP Timers No +LP ADC No +Temperature Yes Internal temperature sensor +Touch Sensor No +eFuse Yes Virtual eFuses supported +================= ======= ================================== + + +Security +-------- + +================= ======= ================================== +Peripheral Support NOTES +================= ======= ================================== +SHA Yes +RSA No +ECC No +HMAC No +TRNG No +ECDSA No +TEE No +APM No +AES No +Digital Signature No +Secure Boot No +XTS_AES No +4096-bit OTP No +PMP/PMA Mo +================= ======= ================================== + +.. note:: + The exact feature availability and default pin mapping depend on the board + and configuration. Consult the board documentation and the + :file:`arch/risc-v/src/common/espressif/Kconfig` for feature flags and + pin selections. + +Supported Boards +================ + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/*
