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commit 745f7542d98dd7ea0203e0c97ef7fb7ff4f55b76 Author: Tiago Medicci Serrano <[email protected]> AuthorDate: Thu Apr 2 16:28:05 2026 -0300 arch/risc-v: Enable low power mode for ESP32-P4 This commit introduces the necessary changes to enable low power mode for ESP32-P4. Please check the corresponding documentation. Signed-off-by: Tiago Medicci Serrano <[email protected]> --- arch/risc-v/src/common/espressif/Kconfig | 181 ++++++++++++++++++++- arch/risc-v/src/common/espressif/Make.defs | 1 + arch/risc-v/src/common/espressif/esp_pm.c | 143 ++++++++++++---- arch/risc-v/src/esp32p4/hal_esp32p4.cmake | 23 ++- arch/risc-v/src/esp32p4/hal_esp32p4.mk | 21 +++ .../esp32p4-function-ev-board/configs/pm/defconfig | 55 +++++++ 6 files changed, 386 insertions(+), 38 deletions(-) diff --git a/arch/risc-v/src/common/espressif/Kconfig b/arch/risc-v/src/common/espressif/Kconfig index 15ae7cc9025..f91c5d80300 100644 --- a/arch/risc-v/src/common/espressif/Kconfig +++ b/arch/risc-v/src/common/espressif/Kconfig @@ -816,25 +816,200 @@ config PM_GPIO_WAKEUP_GPIO27 config PM_GPIO_WAKEUP_GPIO28 bool "GPIO28" - depends on ARCH_CHIP_ESP32C6 + depends on ARCH_CHIP_ESP32C6 || ARCH_CHIP_ESP32P4 default n ---help--- Enable GPIO28 as an GPIO wakeup source. config PM_GPIO_WAKEUP_GPIO29 bool "GPIO29" - depends on ARCH_CHIP_ESP32C6 + depends on ARCH_CHIP_ESP32C6 || ARCH_CHIP_ESP32P4 default n ---help--- Enable GPIO29 as an GPIO wakeup source. config PM_GPIO_WAKEUP_GPIO30 bool "GPIO30" - depends on ARCH_CHIP_ESP32C6 + depends on ARCH_CHIP_ESP32C6 || ARCH_CHIP_ESP32P4 default n ---help--- Enable GPIO30 as an GPIO wakeup source. +config PM_GPIO_WAKEUP_GPIO31 + bool "GPIO31" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO31 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO32 + bool "GPIO32" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO32 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO33 + bool "GPIO33" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO33 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO34 + bool "GPIO34" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO34 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO35 + bool "GPIO35" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO35 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO36 + bool "GPIO36" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO36 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO37 + bool "GPIO37" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO37 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO38 + bool "GPIO38" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO38 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO39 + bool "GPIO39" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO39 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO40 + bool "GPIO40" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO40 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO41 + bool "GPIO41" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO41 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO42 + bool "GPIO42" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO42 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO43 + bool "GPIO43" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO43 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO44 + bool "GPIO44" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO44 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO45 + bool "GPIO45" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO45 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO46 + bool "GPIO46" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO46 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO47 + bool "GPIO47" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO47 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO48 + bool "GPIO48" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO48 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO49 + bool "GPIO49" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO49 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO50 + bool "GPIO50" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO50 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO51 + bool "GPIO51" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO51 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO52 + bool "GPIO52" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO52 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO53 + bool "GPIO53" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO53 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO54 + bool "GPIO54" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO54 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO55 + bool "GPIO55" + depends on ARCH_CHIP_ESP32P4 + default n + ---help--- + Enable GPIO55 as an GPIO wakeup source. + choice PM_GPIO_WAKEUP_TRIGGER_MODE prompt "PM GPIO Wakeup Trigger Mode" default PM_GPIO_WAKEUP_TRIGGER_ANY_LOW diff --git a/arch/risc-v/src/common/espressif/Make.defs b/arch/risc-v/src/common/espressif/Make.defs index d751aa63789..10c8a2aca1a 100644 --- a/arch/risc-v/src/common/espressif/Make.defs +++ b/arch/risc-v/src/common/espressif/Make.defs @@ -279,6 +279,7 @@ include common$(DELIM)espressif$(DELIM)Bootloader.mk # Silent preprocessor warnings CFLAGS += -Wno-shadow -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion -Wno-deprecated-declarations +AFLAGS += -Wno-undef # Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration diff --git a/arch/risc-v/src/common/espressif/esp_pm.c b/arch/risc-v/src/common/espressif/esp_pm.c index 9501106cb2e..f4a9e900826 100644 --- a/arch/risc-v/src/common/espressif/esp_pm.c +++ b/arch/risc-v/src/common/espressif/esp_pm.c @@ -273,97 +273,172 @@ static uint64_t IRAM_ATTR esp_pm_get_gpio_mask(void) { uint64_t io_mask = 0; #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO0 - io_mask |= BIT(0); + io_mask |= BIT64(0); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO1 - io_mask |= BIT(1); + io_mask |= BIT64(1); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO2 - io_mask |= BIT(2); + io_mask |= BIT64(2); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO3 - io_mask |= BIT(3); + io_mask |= BIT64(3); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO4 - io_mask |= BIT(4); + io_mask |= BIT64(4); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO5 - io_mask |= BIT(5); + io_mask |= BIT64(5); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO6 - io_mask |= BIT(6); + io_mask |= BIT64(6); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO7 - io_mask |= BIT(7); + io_mask |= BIT64(7); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO8 - io_mask |= BIT(8); + io_mask |= BIT64(8); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO9 - io_mask |= BIT(9); + io_mask |= BIT64(9); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO10 - io_mask |= BIT(10); + io_mask |= BIT64(10); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO11 - io_mask |= BIT(11); + io_mask |= BIT64(11); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO12 - io_mask |= BIT(12); + io_mask |= BIT64(12); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO13 - io_mask |= BIT(13); + io_mask |= BIT64(13); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO14 - io_mask |= BIT(14); + io_mask |= BIT64(14); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO15 - io_mask |= BIT(15); + io_mask |= BIT64(15); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO16 - io_mask |= BIT(16); + io_mask |= BIT64(16); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO17 - io_mask |= BIT(17); + io_mask |= BIT64(17); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO18 - io_mask |= BIT(18); + io_mask |= BIT64(18); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO19 - io_mask |= BIT(19); + io_mask |= BIT64(19); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO20 - io_mask |= BIT(20); + io_mask |= BIT64(20); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO21 - io_mask |= BIT(21); + io_mask |= BIT64(21); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO22 - io_mask |= BIT(22); + io_mask |= BIT64(22); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO23 - io_mask |= BIT(23); + io_mask |= BIT64(23); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO24 - io_mask |= BIT(24); + io_mask |= BIT64(24); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO25 - io_mask |= BIT(25); + io_mask |= BIT64(25); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO26 - io_mask |= BIT(26); + io_mask |= BIT64(26); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO27 - io_mask |= BIT(27); + io_mask |= BIT64(27); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO28 - io_mask |= BIT(28); + io_mask |= BIT64(28); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO29 - io_mask |= BIT(29); + io_mask |= BIT64(29); #endif #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO30 - io_mask |= BIT(30); + io_mask |= BIT64(30); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO31 + io_mask |= BIT64(31); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO32 + io_mask |= BIT64(32); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO33 + io_mask |= BIT64(33); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO34 + io_mask |= BIT64(34); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO35 + io_mask |= BIT64(35); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO36 + io_mask |= BIT64(36); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO37 + io_mask |= BIT64(37); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO38 + io_mask |= BIT64(38); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO39 + io_mask |= BIT64(39); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO40 + io_mask |= BIT64(40); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO41 + io_mask |= BIT64(41); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO42 + io_mask |= BIT64(42); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO43 + io_mask |= BIT64(43); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO44 + io_mask |= BIT64(44); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO45 + io_mask |= BIT64(45); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO46 + io_mask |= BIT64(46); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO47 + io_mask |= BIT64(47); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO48 + io_mask |= BIT64(48); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO49 + io_mask |= BIT64(49); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO50 + io_mask |= BIT64(50); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO51 + io_mask |= BIT64(51); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO52 + io_mask |= BIT64(52); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO53 + io_mask |= BIT64(53); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO54 + io_mask |= BIT64(54); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO55 + io_mask |= BIT64(55); #endif return io_mask; @@ -386,7 +461,7 @@ static uint64_t IRAM_ATTR esp_pm_get_gpio_mask(void) static void IRAM_ATTR esp_pm_gpio_wakeup_prepare(void) { uint64_t mask_value = esp_pm_get_gpio_mask(); - int pin_mask = 0; + uint64_t pin_mask = 0; # ifdef CONFIG_PM_GPIO_WAKEUP_TRIGGER_ANY_LOW gpio_int_type_t level_mode = GPIO_INTR_LOW_LEVEL; # else @@ -395,10 +470,9 @@ static void IRAM_ATTR esp_pm_gpio_wakeup_prepare(void) for (int i = 0; i < CONFIG_SOC_GPIO_PIN_COUNT; i++) { - pin_mask = BIT(i); + pin_mask = BIT64(i); if ((mask_value & pin_mask) != 0) { - esp_configgpio(i, INPUT); gpio_wakeup_enable(i, level_mode); } } @@ -455,6 +529,7 @@ static void IRAM_ATTR esp_pm_uart_wakeup_prepare(void) #endif }; + esp_sleep_set_console_uart_handling_mode(ESP_SLEEP_ALWAYS_FLUSH_UART); uart_wakeup_setup(uart_num, &wake_up_cfg); esp_sleep_enable_uart_wakeup(uart_num); } diff --git a/arch/risc-v/src/esp32p4/hal_esp32p4.cmake b/arch/risc-v/src/esp32p4/hal_esp32p4.cmake index 3dc54744188..09128dabb13 100644 --- a/arch/risc-v/src/esp32p4/hal_esp32p4.cmake +++ b/arch/risc-v/src/esp32p4/hal_esp32p4.cmake @@ -160,7 +160,8 @@ set(ESP32P4_INCLUDES ${ESP_HAL_3RDPARTY_REPO}/components/upper_hal_dma/src ${ESP_HAL_3RDPARTY_REPO}/components/upper_hal_gpio/include ${ESP_HAL_3RDPARTY_REPO}/components/upper_hal_rmt/include - ${ESP_HAL_3RDPARTY_REPO}/components/upper_hal_rmt/src) + ${ESP_HAL_3RDPARTY_REPO}/components/upper_hal_rmt/src + ${ESP_HAL_3RDPARTY_REPO}/components/upper_hal_uart/include) if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3) list(APPEND ESP32P4_INCLUDES @@ -277,12 +278,15 @@ list( ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_pcnt/${CHIP_SERIES}/pcnt_periph.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_pcnt/pcnt_hal.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_pmu/brownout_hal.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_pmu/${CHIP_SERIES}/pau_hal.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_pmu/${CHIP_SERIES}/pmu_hal.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_rmt/${CHIP_SERIES}/rmt_periph.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_rmt/rmt_hal.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_security/hmac_hal.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_security/sha_hal.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_timg/${CHIP_SERIES}/timer_periph.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_timg/timer_hal.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_touch_sens/touch_sens_hal.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_twai/${CHIP_SERIES}/twai_periph.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_twai/twai_hal_v1.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_uart/${CHIP_SERIES}/uart_periph.c @@ -291,6 +295,7 @@ list( ${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_wdt/wdt_hal_iram.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/adc_share_hw_ctrl.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/clk_ctrl_os.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/clk_utils.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/cpu.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/esp_clk.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/esp_gpio_reserve.c @@ -300,6 +305,9 @@ list( ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/mac_addr.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/mspi/mspi_timing_tuning/mspi_timing_tuning.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/periph_ctrl.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/lowpower/port/${CHIP_SERIES}/sleep_cpu_asm.S + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/lowpower/port/${CHIP_SERIES}/sleep_cpu.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/lowpower/port/${CHIP_SERIES}/sleep_clock.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/cpu_region_protect.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/esp_clk_tree.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/esp_cpu_intr.c @@ -308,17 +316,29 @@ list( ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/pmu_init.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/pmu_param.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/pmu_pvt.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/pmu_sleep.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/rtc_clk_init.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/rtc_clk.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/rtc_time.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/sar_periph_ctrl.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/${CHIP_SERIES}/systimer.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/esp_clk_tree_common.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/pau_regdma.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/port/regdma_link.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/power_supply/brownout.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/power_supply/vbat.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/regi2c_ctrl.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/rtc_module.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/sleep_console.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/sleep_event.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/sleep_gpio.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/sleep_modem.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/sleep_modes.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/sleep_mspi.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/sleep_retention.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/sleep_system_peripheral.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/sleep_uart.c + ${ESP_HAL_3RDPARTY_REPO}/components/esp_hw_support/sleep_usb.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_mm/esp_cache_msync.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_mm/esp_cache_utils.c ${ESP_HAL_3RDPARTY_REPO}/components/esp_mm/esp_mmu_map.c @@ -400,6 +420,7 @@ list( ${ESP_HAL_3RDPARTY_REPO}/components/upper_hal_rmt/src/rmt_encoder.c ${ESP_HAL_3RDPARTY_REPO}/components/upper_hal_rmt/src/rmt_rx.c ${ESP_HAL_3RDPARTY_REPO}/components/upper_hal_rmt/src/rmt_tx.c + ${ESP_HAL_3RDPARTY_REPO}/components/upper_hal_uart/src/uart_wakeup.c ${ESP_HAL_3RDPARTY_REPO}/nuttx/src/components/newlib/newlib/libc/misc/init.c ${ESP_HAL_3RDPARTY_REPO}/nuttx/src/heap_caps.c ${ESP_HAL_3RDPARTY_REPO}/nuttx/src/platform/os.c) diff --git a/arch/risc-v/src/esp32p4/hal_esp32p4.mk b/arch/risc-v/src/esp32p4/hal_esp32p4.mk index 5fa42d34cc5..6b4fb09f477 100644 --- a/arch/risc-v/src/esp32p4/hal_esp32p4.mk +++ b/arch/risc-v/src/esp32p4/hal_esp32p4.mk @@ -156,6 +156,7 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_uart$(DELIM)include # Linker scripts @@ -235,12 +236,15 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)pcnt_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)pau_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)rmt_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)hmac_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)sha_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)$(CHIP_SERIES)$(DELIM)timer_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)touch_sens_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)$(CHIP_SERIES)$(DELIM)twai_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)twai_hal_v1.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)$(CHIP_SERIES)$(DELIM)uart_periph.c @@ -249,6 +253,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)wdt_hal_iram.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)adc_share_hw_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_gpio_reserve.c @@ -258,6 +263,10 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c +CHIP_ASRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)lowpower$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sleep_cpu_asm.S +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)lowpower$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sleep_cpu.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)lowpower$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sleep_clock.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)regdma_link.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_cpu_intr.c @@ -266,17 +275,28 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_param.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_pvt.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_sleep.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sar_periph_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)pau_regdma.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)brownout.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)vbat.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)rtc_module.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_console.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_event.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_gpio.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modes.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_mspi.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modem.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_uart.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_retention.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_system_peripheral.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_usb.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_msync.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_mmu_map.c @@ -358,6 +378,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)uppe CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_rx.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_tx.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_uart$(DELIM)src$(DELIM)uart_wakeup.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)newlib$(DELIM)newlib$(DELIM)libc$(DELIM)misc$(DELIM)init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)heap_caps.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)platform$(DELIM)os.c diff --git a/boards/risc-v/esp32p4/esp32p4-function-ev-board/configs/pm/defconfig b/boards/risc-v/esp32p4/esp32p4-function-ev-board/configs/pm/defconfig new file mode 100644 index 00000000000..72a9c347593 --- /dev/null +++ b/boards/risc-v/esp32p4/esp32p4-function-ev-board/configs/pm/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32p4-function-ev-board" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32P4_FUNCTION_EV_BOARD=y +CONFIG_ARCH_CHIP="esp32p4" +CONFIG_ARCH_CHIP_ESP32P4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PM=y +CONFIG_PM_GOVERNOR_EXPLICIT_RELAX=-1 +CONFIG_PM_GOVERNOR_GREEDY=y +CONFIG_PM_PROCFS=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y
