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commit fc5c01dc7030c627dcc9f334eed06063df3adcc0 Author: Tiago Medicci Serrano <[email protected]> AuthorDate: Tue May 26 13:27:31 2026 +0200 xtensa/esp32: Fix RWDT register offsets. The RWDT register offsets were incorrectly set to ESP32-S3 values instead of ESP32 values. This was introduced when the code was refactored from using the local NuttX header hardware/esp32_rtccntl.h (which had the correct offsets) to using the HAL library headers, and the offsets were moved inline into esp32_wdt.c with wrong values. Correct the offsets to match the actual ESP32 register layout from soc/rtc_cntl_reg.h (RTC_CNTL_WDTCONFIG0_REG at 0x8c, INT_ENA at 0x3c, etc). Without this fix, all RWDT operations (enable, configure timeout, enable interrupt, acknowledge interrupt, feed, write-protect) were targeting wrong memory addresses, rendering the RWDT completely non-functional. Signed-off-by: Tiago Medicci Serrano <[email protected]> --- arch/xtensa/src/esp32/esp32_wdt.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_wdt.c b/arch/xtensa/src/esp32/esp32_wdt.c index b83772a3b01..f1a8d6a139a 100644 --- a/arch/xtensa/src/esp32/esp32_wdt.c +++ b/arch/xtensa/src/esp32/esp32_wdt.c @@ -42,25 +42,25 @@ /* Offset relative to each watchdog timer instance memory base */ -#define RWDT_CONFIG0_OFFSET 0x0098 +#define RWDT_CONFIG0_OFFSET 0x008c #define XTWDT_CONFIG0_OFFSET 0x0060 /* RWDT */ -#define RWDT_STAGE0_TIMEOUT_OFFSET 0x009C -#define RWDT_STAGE1_TIMEOUT_OFFSET 0x00A0 -#define RWDT_STAGE2_TIMEOUT_OFFSET 0x00A4 -#define RWDT_STAGE3_TIMEOUT_OFFSET 0x00A8 -#define RWDT_FEED_OFFSET 0x00AC -#define RWDT_WP_REG 0x00B0 -#define RWDT_INT_ENA_REG_OFFSET 0x0040 -#define RWDT_INT_CLR_REG_OFFSET 0x004c +#define RWDT_STAGE0_TIMEOUT_OFFSET 0x0090 +#define RWDT_STAGE1_TIMEOUT_OFFSET 0x0094 +#define RWDT_STAGE2_TIMEOUT_OFFSET 0x0098 +#define RWDT_STAGE3_TIMEOUT_OFFSET 0x009c +#define RWDT_FEED_OFFSET 0x00a0 +#define RWDT_WP_REG 0x00a4 +#define RWDT_INT_ENA_REG_OFFSET 0x003c +#define RWDT_INT_CLR_REG_OFFSET 0x0048 /* XTWDT */ #define XTWDT_TIMEOUT_OFFSET 0x00f8 #define XTWDT_CLK_PRESCALE_OFFSET 0x00f4 -#define XTWDT_INT_ENA_REG_OFFSET 0x0040 +#define XTWDT_INT_ENA_REG_OFFSET 0x003c /* Helpers for converting from Q13.19 fixed-point format to float */
