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commit fd2fe246cc0fdd575a2c256e2d225cf73cc4bcc8 Author: Piyush Patle <[email protected]> AuthorDate: Wed May 20 08:01:01 2026 +0530 arm64/common: enable EL1 GICv3 sysreg access from EL2 AM62x enters NuttX through EL2 before dropping to EL1. Enable the GICv3 system register interface for lower exception levels during the EL2 handoff so EL1 can use the CPU interface without depending on firmware state. Signed-off-by: Piyush Patle <[email protected]> --- arch/arm64/src/common/arm64_arch.h | 3 ++- arch/arm64/src/common/arm64_boot.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/src/common/arm64_arch.h b/arch/arm64/src/common/arm64_arch.h index fa891ae6361..9ec953800a2 100644 --- a/arch/arm64/src/common/arm64_arch.h +++ b/arch/arm64/src/common/arm64_arch.h @@ -214,7 +214,8 @@ #define ICC_SRE_ELX_SRE_BIT BIT(0) #define ICC_SRE_ELX_DFB_BIT BIT(1) #define ICC_SRE_ELX_DIB_BIT BIT(2) -#define ICC_SRE_EL3_EN_BIT BIT(3) +#define ICC_SRE_ELX_EN_BIT BIT(3) +#define ICC_SRE_EL3_EN_BIT ICC_SRE_ELX_EN_BIT #define ICC_CTLR_EOIMODE_BIT BIT(1) /* ICC SGI macros */ diff --git a/arch/arm64/src/common/arm64_boot.c b/arch/arm64/src/common/arm64_boot.c index 480bfda740f..790bc8b71ea 100644 --- a/arch/arm64/src/common/arm64_boot.c +++ b/arch/arm64/src/common/arm64_boot.c @@ -152,6 +152,17 @@ void arm64_boot_el2_init(void) write_sysreg(reg, hcr_el2); +#if CONFIG_ARM64_GIC_VERSION > 2 + /* Enable EL1 access to the GICv3 system register interface. */ + + reg = read_sysreg(ICC_SRE_EL2); + reg |= (ICC_SRE_ELX_DFB_BIT | /* Disable FIQ bypass */ + ICC_SRE_ELX_DIB_BIT | /* Disable IRQ bypass */ + ICC_SRE_ELX_SRE_BIT | /* System register interface is used */ + ICC_SRE_ELX_EN_BIT); /* Enable lower EL access */ + write_sysreg(reg, ICC_SRE_EL2); +#endif + reg = 0U; /* RES0 */ reg |= CPTR_EL2_RES1; /* RES1 */ reg &= ~(CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */
