casaroli opened a new pull request, #19521:
URL: https://github.com/apache/nuttx/pull/19521
## Summary
Adds support for the external QSPI PSRAM found on RP2350 boards such as the
Pimoroni Pico Plus 2 (8 MiB APS6404 on QMI chip select 1). The RP23xx port
already had the Kconfig scaffolding and the `rp23xx_heaps.c` heap hooks, but
no driver and no build wiring, so `CONFIG_RP23XX_PSRAM` could not actually be
enabled. This completes the feature.
`rp23xx_psramconfig()` assigns the CS1 pin, reads the device ID over the QMI
direct interface to confirm an APS6404-family part (KGD `0x5D`), resets it
into
quad mode, and programs the QMI M1 timing/read/write formats so the region at
`0x11000000` becomes directly addressable and writable. Because driving the
QMI
in direct mode stalls execute-in-place from the flash, the detection and
(re)configuration code runs from RAM (`.time_critical`) with interrupts
disabled; the command bytes are selected with immediates rather than a
`.rodata` table for the same reason (a table lands in flash and faults while
the flash is inaccessible). The register values follow the Raspberry Pi Pico
SDK `setup_psram()`.
`rp23xx_psram_restore()` re-applies the M1 configuration. Writing to the
flash
goes through the bootrom, which reconfigures the shared QMI for chip select 0
and disturbs the PSRAM configuration on chip select 1; the restore hook is
meant to be called from the flash write path after each erase/program.
`rp23xx_heaps.c` is wired into the build and now uses the detected size, so
the
PSRAM is exposed to the memory manager (added to the main heap, used as a
separate heap, or as the user heap) and is skipped cleanly when no PSRAM is
present.
## Impact
* Adds `arch/arm/src/rp23xx/rp23xx_psram.{c,h}` and builds it (plus the
existing `rp23xx_heaps.c`) when `CONFIG_RP23XX_PSRAM=y`.
* Defines the missing `RP23XX_PSRAM` enable option and PSRAM heap-mode choice
in the rp23xx Kconfig, and defines `RP23XX_QMI_BASE` in `rp23xx_qmi.h`
(previously undefined).
* Enables PSRAM by default in the `pimoroni-pico-2-plus:nsh` configuration,
where it adds 8 MiB to the main heap (`CONFIG_MM_REGIONS=2`).
* No change to any board that does not set `CONFIG_RP23XX_PSRAM`.
* Adds a documentation page for the Pimoroni Pico Plus 2.
## Testing
**Host:** macOS (Darwin arm64), `arm-none-eabi-gcc` 15.2.rel1.
**Board:** Pimoroni Pico Plus 2 (RP2350B, 8 MiB APS6404 PSRAM), flashed and
debugged over SWD with a CMSIS-DAP probe (`probe-rs`), console on UART0.
Fresh `./tools/configure.sh pimoroni-pico-2-plus:nsh && make` builds cleanly
and boots to `nsh`.
*Detection and heap* — the 8 MiB is detected and merged into the main heap:
```
nsh> free
total used free maxused maxfree nused nfree name
8906148 7020 8899128 7400 8388592 27 3 Umem
```
*Read/write across the whole 8 MiB* — `ramtest` word, half-word and byte
passes over the PSRAM, all patterns, zero errors:
```
nsh> ramtest -w -a 0x11100000 -s 1048576
RAMTest: Marching ones: ...
RAMTest: Marching zeroes: ...
RAMTest: Pattern test: ... 55555555 aaaaaaaa
RAMTest: Pattern test: ... 66666666 99999999
RAMTest: Pattern test: ... 33333333 cccccccc
RAMTest: Address-in-address test: ...
nsh> (no error lines; repeated with -h and -b)
```
Direct writes/reads at the start, middle and last word of the range
(`0x11000000`, `0x11400000`, `0x117ffffc`) all round-trip.
*Flash-write coexistence and QMI restore* — tested on a branch that also
carries the RP23xx flash MTD + xipfs, with `rp23xx_psram_restore()` called
from
the flash restore path. A file written to xipfs (a real bootrom flash
erase+program) succeeds, and PSRAM keeps working afterwards (pattern intact,
`ramtest` clean). Removing the restore call makes PSRAM return garbage after
the first flash write (`ramtest` fails on every address), confirming the
bootrom flash routines clobber the CS1 configuration and that the restore is
both necessary and correct.
🤖 Generated with [Claude Code](https://claude.com/claude-code)
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