This is an automated email from the ASF dual-hosted git repository.

jerpelea pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git

commit d4d4db5bb1229ec5fd34f2e7bd53ce6185a813ff
Author: zhangyu117 <[email protected]>
AuthorDate: Mon Aug 10 20:05:51 2026 +0800

    arch/tricore: perf.c donot depend on illd
    
    Replace the iLLD helpers IfxCpu_resetAndStartCounters() and
    IfxCpu_getClockCounter() in the performance-counter path with direct
    CSR accesses via tricore_mtcr()/tricore_mfcr().
    
    tricore_reset_ccnt() disables the CPU cycle counter (CPU_CCTRL), clears
    CPU_CCNT, then re-enables it; up_perf_gettime() reads CPU_CCNT directly.
    This removes the arch/tricore perf path's dependency on the Infineon
    iLLD layer. No behavior change.
    
    Signed-off-by: zhangyu117 <[email protected]>
---
 arch/tricore/src/common/tricore_perf.c | 38 +++++++++++++++++++++++++++++++---
 1 file changed, 35 insertions(+), 3 deletions(-)

diff --git a/arch/tricore/src/common/tricore_perf.c 
b/arch/tricore/src/common/tricore_perf.c
index 987c9f12023..03d7f0e2082 100644
--- a/arch/tricore/src/common/tricore_perf.c
+++ b/arch/tricore/src/common/tricore_perf.c
@@ -28,7 +28,16 @@
 #include <nuttx/clock.h>
 #include <nuttx/lib/math32.h>
 
-#include "tricore_internal.h"
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CPU_CCTRL        0xFC00  /* Counter Control */
+#define CPU_CCNT         0xFC04  /* CPU Clock Cycle Count */
+
+/* CPU_CCTRL Count Enable bit. */
+
+#define CCTRL_COUNT_ENABLE (1 << 1)
 
 #ifdef CONFIG_ARCH_PERF_EVENTS
 
@@ -39,6 +48,28 @@
 static unsigned long g_cpu_freq = ULONG_MAX;
 static invdiv_param64_t g_invdiv_param;
 
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void tricore_reset_ccnt(void)
+{
+  uint32_t cctrl = tricore_mfcr(CPU_CCTRL);
+
+  /* Disable and clear the CPU cycle counter */
+
+  cctrl &= ~CCTRL_COUNT_ENABLE;
+  tricore_mtcr(CPU_CCTRL, cctrl);
+  tricore_mtcr(CPU_CCNT, 0);
+  UP_ISB();
+
+  /* Re-enable the CPU cycle counter */
+
+  cctrl |= CCTRL_COUNT_ENABLE;
+  tricore_mtcr(CPU_CCTRL, cctrl);
+  UP_ISB();
+}
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -48,7 +79,8 @@ void up_perf_init(void *arg)
   g_cpu_freq = (unsigned long)(uintptr_t)arg;
 
   invdiv_init_param64(g_cpu_freq, &g_invdiv_param);
-  IfxCpu_resetAndStartCounters(IfxCpu_CounterMode_normal);
+
+  tricore_reset_ccnt();
 }
 
 unsigned long up_perf_getfreq(void)
@@ -58,7 +90,7 @@ unsigned long up_perf_getfreq(void)
 
 clock_t up_perf_gettime(void)
 {
-  return (clock_t)IfxCpu_getClockCounter();
+  return (clock_t)tricore_mfcr(CPU_CCNT);
 }
 
 void up_perf_convert(clock_t elapsed, struct timespec *ts)

Reply via email to