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commit b013f074f492c6d37cf73a85047a11d7414a1bd7 Author: Liam Howatt <[email protected]> AuthorDate: Mon Aug 17 16:16:26 2026 -0400 arch/arm/stm32h5: IWDG remove some ifdefs, extend prescaler. Remove the feature #ifdef guard since the file is conditionally compiled. Remove the #ifdefs for other stm32 families that came from the common stm32_wdg.h. Add additional extended prescaler values for stm32h5 IWDG. Change the WWDG_CFR_WDGTB shift value to match what it should be on stm32h5. (WWDG not supported on stm32h5 yet.) Signed-off-by: Liam Howatt <[email protected]> --- arch/arm/src/stm32h5/hardware/stm32_wdg.h | 55 +++++++++++++++---------------- arch/arm/src/stm32h5/stm32_iwdg.c | 39 +++++++++------------- 2 files changed, 41 insertions(+), 53 deletions(-) diff --git a/arch/arm/src/stm32h5/hardware/stm32_wdg.h b/arch/arm/src/stm32h5/hardware/stm32_wdg.h index 8127a2e4d95..047a2a5d888 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_wdg.h +++ b/arch/arm/src/stm32h5/hardware/stm32_wdg.h @@ -41,9 +41,7 @@ #define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ #define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ #define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ -#if defined(CONFIG_STM32_STM32F30XX) -# define STM32_IWDG_WINR_OFFSET 0x000c /* Window register (32-bit) */ -#endif +#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ #define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ #define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ @@ -55,9 +53,7 @@ #define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET) #define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET) #define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET) -#if defined(CONFIG_STM32_STM32F30XX) -# define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET) -#endif +#define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET) #define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET) #define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET) @@ -77,15 +73,17 @@ /* Prescaler register (32-bit) */ -#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */ -#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT) -# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */ -# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */ -# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */ -# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */ -# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */ -# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */ -# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */ +#define IWDG_PR_SHIFT (0) /* Bits 3-0: Prescaler divider */ +#define IWDG_PR_MASK (15 << IWDG_PR_SHIFT) +# define IWDG_PR_DIV4 ( 0 << IWDG_PR_SHIFT) /* 0000: divider /4 */ +# define IWDG_PR_DIV8 ( 1 << IWDG_PR_SHIFT) /* 0001: divider /8 */ +# define IWDG_PR_DIV16 ( 2 << IWDG_PR_SHIFT) /* 0010: divider /16 */ +# define IWDG_PR_DIV32 ( 3 << IWDG_PR_SHIFT) /* 0011: divider /32 */ +# define IWDG_PR_DIV64 ( 4 << IWDG_PR_SHIFT) /* 0100: divider /64 */ +# define IWDG_PR_DIV128 ( 5 << IWDG_PR_SHIFT) /* 0101: divider /128 */ +# define IWDG_PR_DIV256 ( 6 << IWDG_PR_SHIFT) /* 0110: divider /256 */ +# define IWDG_PR_DIV512 ( 7 << IWDG_PR_SHIFT) /* 0111: divider /512 */ +# define IWDG_PR_DIV1024 ( 8 << IWDG_PR_SHIFT) /* 1xxx: divider /1024 */ /* Reload register (32-bit) */ @@ -98,17 +96,12 @@ #define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */ #define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */ - -#if defined(CONFIG_STM32_STM32F30XX) -# define IWDG_SR_WVU (1 << 2) /* Bit 2: */ -#endif +#define IWDG_SR_WVU (1 << 2) /* Bit 2: Watchdog counter window value update */ /* Window register (32-bit) */ -#if defined(CONFIG_STM32_STM32F30XX) -# define IWDG_WINR_SHIFT (0) -# define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT) -#endif +#define IWDG_WINR_SHIFT (0) +#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT) /* Control Register (32-bit) */ @@ -122,12 +115,16 @@ #define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */ #define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT) -#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */ -#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT) -# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */ -# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */ -# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */ -# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */ +#define WWDG_CFR_WDGTB_SHIFT (11) /* Bits 13:11 [2:0]: Timer Base */ +#define WWDG_CFR_WDGTB_MASK (7 << WWDG_CFR_WDGTB_SHIFT) +# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 000: CK Counter Clock (PCLK1 div 4096) div 1 */ +# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 001: CK Counter Clock (PCLK1 div 4096) div 2 */ +# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 010: CK Counter Clock (PCLK1 div 4096) div 4 */ +# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 011: CK Counter Clock (PCLK1 div 4096) div 8 */ +# define WWDG_CFR_PCLK1d16 (4 << WWDG_CFR_WDGTB_SHIFT) /* 100: CK Counter Clock (PCLK1 div 4096) div 16 */ +# define WWDG_CFR_PCLK1d32 (5 << WWDG_CFR_WDGTB_SHIFT) /* 101: CK Counter Clock (PCLK1 div 4096) div 32 */ +# define WWDG_CFR_PCLK1d64 (6 << WWDG_CFR_WDGTB_SHIFT) /* 110: CK Counter Clock (PCLK1 div 4096) div 64 */ +# define WWDG_CFR_PCLK1d128 (7 << WWDG_CFR_WDGTB_SHIFT) /* 111: CK Counter Clock (PCLK1 div 4096) div 128 */ #define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */ diff --git a/arch/arm/src/stm32h5/stm32_iwdg.c b/arch/arm/src/stm32h5/stm32_iwdg.c index c4a4820e45a..0898ff1d1bd 100644 --- a/arch/arm/src/stm32h5/stm32_iwdg.c +++ b/arch/arm/src/stm32h5/stm32_iwdg.c @@ -43,8 +43,6 @@ #include "hardware/stm32_dbgmcu.h" #include "stm32_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -53,7 +51,7 @@ /* The minimum frequency of the IWDG clock is: * - * Fmin = Flsi / 256 + * Fmin = Flsi / 1024 * * So the maximum delay (in milliseconds) is then: * @@ -62,11 +60,11 @@ * For example, if Flsi = 30Khz (the nominal, uncalibrated value), then the * maximum delay is: * - * Fmin = 117.1875 - * 1000 * 4095 / Fmin = 34,944 MSec + * Fmin = 29.296875 + * 1000 * 4095 / Fmin = 139,776 MSec */ -#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256) +#define IWDG_FMIN (STM32_LSI_FREQUENCY / 1024) #define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN) /* Configuration ************************************************************/ @@ -527,14 +525,16 @@ static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, for (prescaler = 0; ; prescaler++) { - /* PR = 0 -> Divider = 4 = 1 << 2 - * PR = 1 -> Divider = 8 = 1 << 3 - * PR = 2 -> Divider = 16 = 1 << 4 - * PR = 3 -> Divider = 32 = 1 << 5 - * PR = 4 -> Divider = 64 = 1 << 6 - * PR = 5 -> Divider = 128 = 1 << 7 - * PR = 6 -> Divider = 256 = 1 << 8 - * PR = n -> Divider = 1 << (n+2) + /* PR = 0 -> Divider = 4 = 1 << 2 + * PR = 1 -> Divider = 8 = 1 << 3 + * PR = 2 -> Divider = 16 = 1 << 4 + * PR = 3 -> Divider = 32 = 1 << 5 + * PR = 4 -> Divider = 64 = 1 << 6 + * PR = 5 -> Divider = 128 = 1 << 7 + * PR = 6 -> Divider = 256 = 1 << 8 + * PR = 7 -> Divider = 512 = 1 << 9 + * PR = 8 -> Divider = 1024 = 1 << 10 + * PR = n -> Divider = 1 << (n+2) */ shift = prescaler + 2; @@ -558,7 +558,7 @@ static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, * settings. */ - if (reload <= IWDG_RLR_MAX || prescaler == 6) + if (reload <= IWDG_RLR_MAX || prescaler == 8) { /* Note that we explicitly break out of the loop rather than using * the 'for' loop termination logic because we do not want the @@ -686,18 +686,9 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ defined(CONFIG_STM32_JTAG_SW_ENABLE) { -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); cr |= DBGMCU_APB1_IWDGSTOP; putreg32(cr, STM32_DBGMCU_APB1_FZ); -#else /* if defined(CONFIG_STM32_STM32F10XX) */ - uint32_t cr = getreg32(STM32_DBGMCU_CR); - cr |= DBGMCU_CR_IWDGSTOP; - putreg32(cr, STM32_DBGMCU_CR); -#endif } #endif } - -#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */
