dcgong2917 opened a new pull request, #19989:
URL: https://github.com/apache/nuttx/pull/19989
## Summary
This PR adds a NuttX watchdog lower-half for the Ameba KM4 non-secure
system
watchdog (WDG2) and registers it as `/dev/watchdog0`. The same driver is
wired
into three Ameba ICs: RTL8721Dx, RTL8720F and RTL8721F.
The driver follows the data-driven chip-header pattern already used by the
other Ameba peripheral drivers in this port (GPIO, UART, I2C, SPI, PWM,
ADC and
RTC). The shared core, `arch/arm/src/common/ameba/ameba_wdg.c` and its
header
`ameba_wdg.h`, implements the whole `struct watchdog_lowerhalf_s` (start,
stop,
keepalive, getstatus, settimeout and capture) on top of the vendor fwlib
WDG
API. Those fwlib entry points are ROM-resident, so no `board.mk` change is
required.
Each IC contributes only its WDG2 register base and IRQ number through a
small
`ameba_wdg_chip.h`; the shared core is identical across the three and
needs no
change to port to a future Ameba IC. The per-chip values, verified against
each
SoC's `hal_platform.h` and `ameba_vector_table.h`, are:
| IC | WDG2 base | non-secure system WDG IRQ |
| --------- | ------------ | ------------------------- |
| RTL8721Dx | `0x41008D80` | `KM4_NS_WDG` (65) |
| RTL8720F | `0x40801D80` | `KM4TZ_NS_WDG` (52) |
| RTL8721F | `0x4080AD80` | `CPU0_NS_WDG` (69) |
WDG2 cannot be halted once it has been enabled, so the standard watchdog
semantics are modelled around that constraint using the hardware early
interrupt (EI). `stop()` is emulated by letting the EI auto-refresh the
counter
so the timeout never elapses, and `capture()` delivers a pre-timeout
callback to
the application through the same EI.
The EI has a three-part timing contract, all handled in the driver. First,
it
must be armed with `EIMOD = ENABLE` at `WDG_Init` time. Second, its `EIE`
gate
only takes effect after `WDG_Enable`. Third, because the EI is
level-based, a
pure `capture()` path must mask `EIE` after the one-shot callback;
otherwise it
re-enters and storms while the reset is pending. The EI flag is cleared
twice to
account for the slow WDG clock domain.
## Impact
This is a new, opt-in driver gated by the new `CONFIG_AMEBA_WDG` Kconfig
entry
under `arch/arm/src/common/ameba`, and it is disabled by default, so no
existing
configuration or board behavior changes.
In addition to the driver, the PR adds a `wdg` board configuration, the
board
bring-up registration and the board documentation (`index.rst`) for each
of the
three EVBs (pke8721daf, rtl8720f_evb and rtl8721f_evb). It also adds the
`WDG_`
prefix to the `tools/nxstyle.c` mixed-case whitelist, since the fwlib API
is
camel-case (`WDG_Init`, `WDG_Refresh`, `WDG_INTConfig` and so on),
consistent
with the existing `GPIO_`, `UART_` and `RTIM_` entries. Finally, it
corrects the
RTL8720F row in the rtl8721dx chip-header reference table, where the
non-secure
system WDG IRQ is `KM4TZ_NS_WDG` (52).
## Testing
The driver was hardware-verified on all three boards. On each board the
`apps/examples/watchdog` (`wdog`) example was run, and the timeout reset,
`stop()` and `capture()` behaviors were confirmed.
Host: Ubuntu (WSL2). Boards and logs:
- pke8721daf (RTL8721Dx): timeout reset (`KM4 BOOT REASON 80: WDG2`),
`stop()`
keeping the board alive, and `capture()` firing roughly `EICNT` ms
before the
reset.
- rtl8720f_evb (RTL8720F): timeout reset (`AP BOOT REASON 80 / WDG2_GLB`),
`stop()`, and `capture()`.
- rtl8721f_evb (RTL8721F): timeout reset (`AP BOOT REASON 80 / WDG2_GLB`),
`stop()`, and `capture()`.
For CI hygiene, `./tools/checkpatch.sh` passes on all three commits, the
three
`wdg` defconfigs are `make savedefconfig`-equivalent, and the build was
verified
for both the Make and CMake flows.
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