imeghar2408-max opened a new pull request, #20012:
URL: https://github.com/apache/nuttx/pull/20012

   ## Summary
   
   Fix the assignment of RISC-V per-CPU data so that each HART is assigned
   the `g_percpu` entry corresponding to its logical CPU ID.
   
   Previously, `riscv_percpu_init()` initialized interrupt stacks according
   to the `g_percpu[]` array index and placed the entries in a FIFO freelist.
   `riscv_percpu_add_hart()` then assigned entries by freelist order, which
   made the per-CPU entry depend on the order in which HARTs registered.
   
   When HART boot order differs from logical CPU order, this can associate a
   HART with the wrong per-CPU interrupt stack. This is inconsistent with
   the CPU-indexed interrupt stack handling used elsewhere in the RISC-V
   architecture.
   
   This change uses `riscv_hartid_to_cpuid()` to select the corresponding
   `g_percpu[]` entry directly and removes the now-unused freelist.
   
   ## Impact
   
   This change affects:
   
   `arch/risc-v/src/common/riscv_percpu.c`
   
   It makes per-CPU and interrupt-stack assignment deterministic with
   respect to the logical CPU ID, independent of HART boot order.
   
   No public API changes are introduced.
   
   ## Testing
   
   Built and boot-tested with:
   
   - Configuration: `rv-virt:ksmp64`
   - Architecture: RISC-V 64-bit SMP
   - Toolchain: `riscv-none-elf-gcc`
   - Build result: `BUILD EXIT CODE: 0`
   - QEMU: 4 CPUs
   
   QEMU runtime testing showed all four CPUs booting successfully. The
   reported interrupt stack bases were:
   
   - CPU0: `0x80408800`
   - CPU1: `0x80408000`
   - CPU2: `0x80407800`
   - CPU3: `0x80407000`
   
   with 2048-byte spacing between consecutive CPU interrupt stacks, matching
   the expected CPU-indexed layout.
   
   The QEMU configuration uses the normal ascending HART startup order, so
   the test verifies the deterministic mapping and normal SMP boot but does
   not directly reproduce a reordered HART boot sequence.
   
   Fixes: #19875


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