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new e1ac5079d2d arch/arm/stm32f4: fudge STM32F411VE NGPIO so GPIOH is
enabled
e1ac5079d2d is described below
commit e1ac5079d2df69a8881825378dc9a01bd8c72f51
Author: Jacob Dahl <[email protected]>
AuthorDate: Sat Aug 29 14:39:41 2026 -0600
arch/arm/stm32f4: fudge STM32F411VE NGPIO so GPIOH is enabled
STM32_NGPIO_PORTS is (N+15)>>4. 81 (the real pin count) yields six
ports A-F, so PH0/PH1 cannot be configured. 113 matches the F40x
100-pin entries and gives A-H.
Signed-off-by: Jacob Dahl <[email protected]>
---
arch/arm/include/stm32f4/chip.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/stm32f4/chip.h b/arch/arm/include/stm32f4/chip.h
index 796e1590ab4..9bf947fa6fc 100644
--- a/arch/arm/include/stm32f4/chip.h
+++ b/arch/arm/include/stm32f4/chip.h
@@ -215,7 +215,7 @@
# define STM32_NSDIO 1 /* One SDIO interface */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS (only) */
-# define STM32_NGPIO 81 /* GPIOA-H */
+# define STM32_NGPIO 113 /* GPIOA-H. (N+15)>>4 is the port
count; 81 yields A-F and drops H. */
# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */
# define STM32_NDAC 0 /* No DAC */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels
*/
