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commit 3270e9584e537d3f28c3b4da9d1a7cac19c91141 Author: raiden00pl <[email protected]> AuthorDate: Mon Sep 7 13:25:42 2026 +0200 arch/intel64: keep the HPET ISR attached when the timer is stopped intel64_hpet_setisr() with a NULL handler detached the ISR with irq_attach(irq, NULL), which installs irq_unexpected_isr(). The oneshot driver does this every time the timer expires or is re-armed, so an HPET interrupt already in flight to another CPU lands on the unexpected ISR and panics the system: irq_unexpected_isr: ERROR irq: 34 seen under SMP with the LTP test suite. Just mask the interrupt and keep the ISR attached; intel64_oneshot_handler() already treats an interrupt that arrives while the timer is not running as spurious. Assisted-by: Claude Code Signed-off-by: raiden00pl <[email protected]> --- arch/x86_64/src/intel64/intel64_hpet.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86_64/src/intel64/intel64_hpet.c b/arch/x86_64/src/intel64/intel64_hpet.c index 4e993c27830..36512ac6c71 100644 --- a/arch/x86_64/src/intel64/intel64_hpet.c +++ b/arch/x86_64/src/intel64/intel64_hpet.c @@ -390,9 +390,12 @@ static int intel64_hpet_setisr(struct intel64_tim_dev_s *dev, uint8_t timer, if (handler == NULL) { - /* Disable interrupt */ + /* Disable the interrupt but keep the ISR attached. Detaching it here + * installs irq_unexpected_isr(), and an HPET interrupt that is already + * in flight to another CPU then panics the system. A stray interrupt + * is handled as spurious by the oneshot ISR instead. + */ - irq_attach(irq, handler, arg); up_disable_irq(irq); } else
