darrylring opened a new pull request, #20122:
URL: https://github.com/apache/nuttx/pull/20122

   ## Summary
   
   This adds basic MPU support for the STM32H5 based on the initialization in 
the STM32U5 (same core).
   
   The STM32H5 has a couple issues ("features") related to the OTP flash region:
   
   1. It cannot be accessed via cacheable reads. If ICACHE is enabled, reading 
OTP will cause a hard fault.
   2. Reading unwritten OTP flash causes flash double ECC errors, which 
triggers NMIs by default. This crashes NuttX currently. (This is out of scope 
for this PR.)
   
   **NOTE: This does not enable protected mode builds 
(`CONFIG_BUILD_PROTECTED`) at this time.** I don't currently understand that 
portion of the codebase enough (yet) to attempt that.
   
   ## Impact
   
   No impact, since MPU support is currently not implemented.
   
   ## Testing
   
   I added code to the NUCLEO-H563ZI board to configure an MPU region over the 
OTP flash in the case that `CONFIG_ARM_MPU` and `CONFIG_STM32_ICACHE` are 
enabled. I have not added these to any `defconfig`, though.
   
   
   Before, with `CONFIG_STM32_ICACHE` disabled:
   
   ```
   nsh> mh 0x08FFF800 0xC
     0x8fff800 = 0x003e
     0x8fff802 = 0x0063
     0x8fff804 = 0x5111
     0x8fff806 = 0x3332
     0x8fff808 = 0x3236
     0x8fff80a = 0x3836
   ```
   
   Before, with `CONFIG_STM32_ICACHE` enabled:
   
   ```
   nsh> mh 0x08FFF800 0xC
   dump_assert_info: Current Version: NuttX  13.0.1-RC1 3a8b290f71-dirty Sep 11 
2026 16:26:21 arm
   dump_assert_info: Assertion failed panic: at file: 
armv8-m/arm_hardfault.c:147 task: <noname> process: <noname> 0x8012db5
   up_dump_register: R0: 00000000 R1: 080150bb R2: 00000000  R3: 08fff800
   up_dump_register: R4: 08014ce5 R5: 08014a19 R6: 0801a3e7  FP: 00000000
   up_dump_register: R8: 00000000 SB: 00000000 SL: 20003f18 R11: 00000000
   up_dump_register: IP: 00000000 SP: 20004448 LR: 0801508d  PC: 080150d2
   up_dump_register: xPSR: 81000000 BASEPRI: 00000000 CONTROL: 00000000
   up_dump_register: EXC_RETURN: ffffffac
   ...
   ```
   
   After, with `CONFIG_ARM_MPU` and `CONFIG_STM32_ICACHE` enabled:
   
   ```
   nsh> mh 0x08FFF800 0xC
     0x8fff800 = 0x003e
     0x8fff802 = 0x0063
     0x8fff804 = 0x5111
     0x8fff806 = 0x3332
     0x8fff808 = 0x3236
     0x8fff80a = 0x3836
   ```


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