gemstonedevteam opened a new pull request, #20137:
URL: https://github.com/apache/nuttx/pull/20137
> Opening as draft since this depends on #20136 will mark ready once that
lands.
### Summary
* Adds a PWM lower-half driver for the AM67 EPWM instances, covering both
output channels (EPWMxA and EPWMxB) of EPWM0 and EPWM1.
* The time-base is clocked from the EPWM functional clock, period in
`TBPRD`
and duty in `CMPA`/`CMPB`, with the action-qualifier configured for
standard
edge-aligned output: set on zero, clear on compare.
* The CTRL_MMR EPWM clock enables are unlocked once during board bring-up
before any instance is configured.
* t3-gem-o1 registers EPWM0 as `/dev/pwm0` and EPWM1 as `/dev/pwm1`, with
`CONFIG_PWM_NCHANNELS=2` so both channels are reachable through one
device.
### Impact
* Is new feature added? **YES** — PWM support for AM67.
* Impact on user? **NO** — new driver, opt-in by Kconfig.
* Impact on build? **NO**.
* Impact on hardware? **YES** — arch/arm/am67 and board t3-gem-o1.
* Impact on documentation? **YES** — provided in this PR (second commit).
* Impact on security? **NO**.
* Impact on compatibility? **NO** — additive.
* Anything else? Depends on PRs 3–4.
### Testing
```
Build Host(s): Pardus GNU/Linux 25 (Debian 13 base), x86_64, host gcc 14
Toolchain: arm-none-eabi-gcc 14.2.1 20241119 (15:14.2.rel1-1)
Target: arm / TI AM67 (J722S) Cortex-R5F, board t3-gem-o1:nsh
nuttx-apps: 5a7ab4200
Loaded on the main-domain R5F by Linux remoteproc; console on UART-MAIN1.
```
Testing logs before change: no PWM support on this arch.
The version string in the logs is from the tested build; the commits were
GPG-signed afterwards, which rewrites hashes. The code is unchanged.
Testing logs after change:
```
make distclean && ./tools/configure.sh t3-gem-o1:nsh && make -j
-> nuttx ELF 541496 bytes, 0 compiler warnings
Console:
nsh> pwm -p /dev/pwm0 -f 1000 -d 50 -t 1
pwm_main: starting output with frequency: 1000 channel: 1 duty: 00007fff
channel: 2 duty: 00007fff
pwm_main: stopping output
nsh> pwm -p /dev/pwm1 -f 1000 -d 50 -t 1
pwm_main: starting output with frequency: 1000 channel: 1 duty: 00007fff
channel: 2 duty: 00007fff
pwm_main: stopping output
nsh>
Test plan result:
console_alive PASS prompt responsive
version PASS NuttX version 0.0.0 d4055f59a2 Sep 10 2026
13:48:45 t3-gem-o1:nsh
procfs PASS procfs readable
tasks PASS 2 task lines
dev_nodes PASS all expected nodes present
pwm_pwm0 PASS /dev/pwm0 1 kHz / 50% for 1 s
pwm_pwm1 PASS /dev/pwm1 1 kHz / 50% for 1 s
PASS=7
```
Measured time base, captured 2026-09-11. The log above only shows the ioctl
returning; this reads the registers back from the A53 over `/dev/mem` while
NuttX is driving the output.
```
NuttX: nsh> pwm -p /dev/pwm0 -f 1000 -d 50 -t 25 &
A53, while that is running (32-bit reads: the peripheral returns 0 for an
8-bit access, so the 16-bit registers are taken as halves of a word):
0x23000000 = 67640 -> TBCTL = 0x0838
0x23000008 = 4095981386 -> TBCNT = 46922, TBPRD = 62499
0x23000010 = 2047934464 -> CMPA = 31249
TBCTL 0x0838: HSPCLKDIV field 0 -> divider 1, CLKDIV field 2 -> divider 4
frequency = 250 MHz / (1 * 4 * (62499 + 1)) = 1000.00 Hz
duty = 31249 / 62500 = 49.998 %
TBCNT sampled twice 0.4 s apart: 62272 -> 61319, so the time base is
clocked and running, not merely loaded.
/dev/pwm1 at 0x23010000 reads identically: TBCTL 0x0838, TBPRD 62499,
CMPA 31249 -> 1000.00 Hz, 49.998 %, TBCNT 46456 -> 8224.
CTRLMMR_EPWM_TB_CLKEN (0x00104130) = 0x5, so the EPWM0 clock gate the
driver opens during bring-up is in fact open.
```
### PR verification Self-Check
* [x] This PR introduces only one functional change.
* [x] I have updated all required description fields above.
* [x] My PR adheres to Contributing Guidelines and Documentation.
* [ ] My PR is still work in progress (not ready for review).
* [x] My PR is ready for review and can be safely merged into a codebase.
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: [email protected]
For queries about this service, please contact Infrastructure at:
[email protected]
