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commit 27d948a27f8a12e1803acb3c03d6df135c3aa1c3 Author: Liam Howatt <[email protected]> AuthorDate: Fri Sep 18 16:12:24 2026 -0400 Documentation/stm32h5: board.h clock defines. Document the board.h keep-HSI-running-in-stop-mode define STM32_BOARD_HSIKERON_ENABLE and the USART clock source selection defines. Signed-off-by: Liam Howatt <[email protected]> --- Documentation/platforms/arm/stm32h5/index.rst | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/platforms/arm/stm32h5/index.rst b/Documentation/platforms/arm/stm32h5/index.rst index ac6f0b71ab0..ee1768faf9b 100644 --- a/Documentation/platforms/arm/stm32h5/index.rst +++ b/Documentation/platforms/arm/stm32h5/index.rst @@ -135,6 +135,26 @@ of the block size and count when partitioning the OTP area for their needs. ``len`` is the number of bytes - not words. It has no alignment requirement. ``offset`` is the offset in bytes. It must be a multiple of 4. +Clocks +------ + +``STM32_BOARD_HSIKERON_ENABLE`` can be defined in board.h to keep HSI running in +STOP mode. This can be used to keep a peripheral clocked by HSI running in +STOP mode. + +``STM32_RCC_CCIPR1_U[S]ARTxSEL`` (e.g. ``STM32_RCC_CCIPR1_USART3SEL``) can be defined as one of + +- ``RCC_CCIPR1_U[S]ARTxSEL_RCCPCLK1`` +- ``RCC_CCIPR1_U[S]ARTxSEL_PLL2QCK`` +- ``RCC_CCIPR1_U[S]ARTxSEL_PLL3QCK`` +- ``RCC_CCIPR1_U[S]ARTxSEL_HSIKERCK`` +- ``RCC_CCIPR1_U[S]ARTxSEL_CSIKERCK`` +- ``RCC_CCIPR1_U[S]ARTxSEL_LSECK`` + +E.g. ``RCC_CCIPR1_USART3SEL_HSIKERCK`` in board.h to select the clock source for that USART. +The clock source is set in RCC initialization. Only stm32_serial.c is aware of this setting. +TODO: Make stm32_lowputc.c aware of this clock source setting too. + References ================= [RM0481] Reference Manual: STM32H523/33xx, STM32H562/63xx, and STM32H573xx Arm® -based 32-bit MCUs
