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The following commit(s) were added to refs/heads/master by this push:
new c1938018e87 arch/arm/stm32h7: fix the bit of ETH_MTLOMR_DTXSTS.
c1938018e87 is described below
commit c1938018e876c1a6b57e529c9a8f6d09023bd71e
Author: Daniel P. Carvalho <[email protected]>
AuthorDate: Sun Sep 20 18:21:04 2026 -0300
arch/arm/stm32h7: fix the bit of ETH_MTLOMR_DTXSTS.
The Drop Transmit Status field of the MTL operation mode register is
bit 1, but it was defined as bit 0. The driver does not use it.
Signed-off-by: Daniel P. Carvalho <[email protected]>
Assisted-by: Claude:claude-sonnet-5
---
arch/arm/src/stm32h7/hardware/stm32_ethernet.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h
b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h
index efb5e91071b..5765047abe4 100644
--- a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h
@@ -316,7 +316,7 @@
/* Ethernet MTL registers */
-#define ETH_MTLOMR_DTXSTS (1 << 0) /* Bit 0: Drop Transmit
Status */
+#define ETH_MTLOMR_DTXSTS (1 << 1) /* Bit 1: Drop Transmit
Status */
#define ETH_MTLOMR_CNTPRST (1 << 8) /* Bit 8: Counters Preset */
#define ETH_MTLOMR_CNTCLR (1 << 9) /* Bit 9: Counters Reset */
