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commit cc8c7d07691d549542661d3d7d6a34ad710e985c Author: raiden00pl <[email protected]> AuthorDate: Wed Aug 26 10:05:11 2026 +0200 arch/arm/stm32l5: Use common Cortex-M33 GPIO and EXTI drivers Select STM32_HAVE_IP_GPIO_M33_V1 and STM32_HAVE_IP_EXTI_M33_V1 and drop the family GPIO and EXTI sources and headers in favor of the common Cortex-M33 v1 implementation. Define both EXTI register banks and retain the named bit definitions. Use shared line and selector helpers without per-line conditionals. Clear each GPIO selector with the same byte mask, as the H5 driver does. Cover both 32-bit banks and H5 line inventories for later migration. The common EXTI driver also routes the selected port through EXTICR, which the family driver never programmed, so GPIO interrupts now work on ports other than GPIOA. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- .../src/common/stm32/hardware/stm32_exti_m33_v1.h | 1120 +++++++++++++------- arch/arm/src/common/stm32/stm32_exti_gpio_m33_v1.c | 14 +- arch/arm/src/stm32l5/CMakeLists.txt | 2 - arch/arm/src/stm32l5/Kconfig | 2 + arch/arm/src/stm32l5/Make.defs | 2 +- arch/arm/src/stm32l5/hardware/stm32l5_exti.h | 121 --- arch/arm/src/stm32l5/hardware/stm32l5_gpio.h | 389 ------- arch/arm/src/stm32l5/stm32.h | 2 +- arch/arm/src/stm32l5/stm32l5_dumpgpio.c | 2 +- arch/arm/src/stm32l5/stm32l5_exti.h | 155 --- arch/arm/src/stm32l5/stm32l5_exti_gpio.c | 186 ---- arch/arm/src/stm32l5/stm32l5_gpio.c | 408 ------- arch/arm/src/stm32l5/stm32l5_gpio.h | 365 ------- arch/arm/src/stm32l5/stm32l5_lowputc.c | 2 +- arch/arm/src/stm32l5/stm32l5_serial.c | 2 +- arch/arm/src/stm32l5/stm32l5_spi.c | 2 +- arch/arm/src/stm32l5/stm32l5_start.c | 2 +- arch/arm/src/stm32l5/stm32l5_tim.c | 2 +- .../arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h | 2 +- .../arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c | 2 +- boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c | 2 +- .../arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c | 2 +- .../arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c | 2 +- .../arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c | 2 +- .../arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c | 2 +- .../arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c | 2 +- .../arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h | 2 +- 27 files changed, 764 insertions(+), 2032 deletions(-) diff --git a/arch/arm/src/common/stm32/hardware/stm32_exti_m33_v1.h b/arch/arm/src/common/stm32/hardware/stm32_exti_m33_v1.h index b97f79f5a24..ec9cf3315bb 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_exti_m33_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_exti_m33_v1.h @@ -34,9 +34,11 @@ * Pre-processor Definitions ****************************************************************************/ -/* EXTI Line Inventory ******************************************************/ +/* EXTI line inventory. */ -#if defined(CONFIG_STM32_STM32U3C5XX) +#if defined(CONFIG_STM32_STM32L562XX) +# define STM32_EXTI_NLINES 43 +#elif defined(CONFIG_STM32_STM32U3C5XX) # define STM32_EXTI_NLINES 23 #elif defined(CONFIG_STM32_STM32U585XX) # define STM32_EXTI_NLINES 24 @@ -44,10 +46,22 @@ # define STM32_EXTI_NLINES 26 #elif defined(CONFIG_ARCH_CHIP_STM32C5) # define STM32_EXTI_NLINES 36 +#elif defined(CONFIG_STM32_STM32H50XXX) +# define STM32_EXTI_NLINES 54 +#elif defined(CONFIG_STM32_STM32H53XXX) +# define STM32_EXTI_NLINES 59 +#elif defined(CONFIG_STM32_STM32H563XX) +# define STM32_EXTI_NLINES 58 #else # error "Unsupported STM32 M33 EXTI line inventory" #endif +/* Register availability and implemented lines depend on the chip. Some + * chips omit bank 2, security or lock registers. The shared layout below + * does not imply that every register or line is implemented. In particular, + * direct lines do not have trigger or pending bits. + */ + /* Register Offsets *********************************************************/ #define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */ @@ -57,6 +71,13 @@ #define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */ #define STM32_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */ #define STM32_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */ +#define STM32_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */ +#define STM32_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */ +#define STM32_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */ +#define STM32_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */ #define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */ #define STM32_EXTI_EXTICR2_OFFSET 0x0064 /* External Interrupt Selection 2 */ #define STM32_EXTI_EXTICR3_OFFSET 0x0068 /* External Interrupt Selection 3 */ @@ -64,6 +85,8 @@ #define STM32_EXTI_LOCKR_OFFSET 0x0070 /* Lock */ #define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */ #define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */ +#define STM32_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */ +#define STM32_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */ /* Register Addresses *******************************************************/ @@ -74,6 +97,13 @@ #define STM32_EXTI_FPR1 (STM32_EXTI_BASE + STM32_EXTI_FPR1_OFFSET) #define STM32_EXTI_SECCFGR1 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR1_OFFSET) #define STM32_EXTI_PRIVCFGR1 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_RPR2 (STM32_EXTI_BASE + STM32_EXTI_RPR2_OFFSET) +#define STM32_EXTI_FPR2 (STM32_EXTI_BASE + STM32_EXTI_FPR2_OFFSET) +#define STM32_EXTI_SECCFGR2 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR2_OFFSET) +#define STM32_EXTI_PRIVCFGR2 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR2_OFFSET) #define STM32_EXTI_EXTICR1 (STM32_EXTI_BASE + STM32_EXTI_EXTICR1_OFFSET) #define STM32_EXTI_EXTICR2 (STM32_EXTI_BASE + STM32_EXTI_EXTICR2_OFFSET) #define STM32_EXTI_EXTICR3 (STM32_EXTI_BASE + STM32_EXTI_EXTICR3_OFFSET) @@ -81,390 +111,720 @@ #define STM32_EXTI_LOCKR (STM32_EXTI_BASE + STM32_EXTI_LOCKR_OFFSET) #define STM32_EXTI_IMR1 (STM32_EXTI_BASE + STM32_EXTI_IMR1_OFFSET) #define STM32_EXTI_EMR1 (STM32_EXTI_BASE + STM32_EXTI_EMR1_OFFSET) +#define STM32_EXTI_IMR2 (STM32_EXTI_BASE + STM32_EXTI_IMR2_OFFSET) +#define STM32_EXTI_EMR2 (STM32_EXTI_BASE + STM32_EXTI_EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ -/* EXTI rising trigger selection register */ - -#define EXTI_RTSR1_RT0 (1 << 0) -#define EXTI_RTSR1_RT1 (1 << 1) -#define EXTI_RTSR1_RT2 (1 << 2) -#define EXTI_RTSR1_RT3 (1 << 3) -#define EXTI_RTSR1_RT4 (1 << 4) -#define EXTI_RTSR1_RT5 (1 << 5) -#define EXTI_RTSR1_RT6 (1 << 6) -#define EXTI_RTSR1_RT7 (1 << 7) -#define EXTI_RTSR1_RT8 (1 << 8) -#define EXTI_RTSR1_RT9 (1 << 9) -#define EXTI_RTSR1_RT10 (1 << 10) -#define EXTI_RTSR1_RT11 (1 << 11) -#define EXTI_RTSR1_RT12 (1 << 12) -#define EXTI_RTSR1_RT13 (1 << 13) -#define EXTI_RTSR1_RT14 (1 << 14) -#define EXTI_RTSR1_RT15 (1 << 15) -#define EXTI_RTSR1_RT16 (1 << 16) -#define EXTI_RTSR1_RT17 (1 << 17) -#define EXTI_RTSR1_RT18 (1 << 18) -#define EXTI_RTSR1_RT19 (1 << 19) -#define EXTI_RTSR1_RT20 (1 << 20) -#define EXTI_RTSR1_RT21 (1 << 21) -#define EXTI_RTSR1_RT22 (1 << 22) -#if STM32_EXTI_NLINES > 23 -#define EXTI_RTSR1_RT23 (1 << 23) -#endif -#if STM32_EXTI_NLINES > 24 -#define EXTI_RTSR1_RT24 (1 << 24) -#endif -#if STM32_EXTI_NLINES > 25 -#define EXTI_RTSR1_RT25 (1 << 25) -#endif - -/* EXTI falling trigger selection register */ - -#define EXTI_FTSR1_FT0 (1 << 0) -#define EXTI_FTSR1_FT1 (1 << 1) -#define EXTI_FTSR1_FT2 (1 << 2) -#define EXTI_FTSR1_FT3 (1 << 3) -#define EXTI_FTSR1_FT4 (1 << 4) -#define EXTI_FTSR1_FT5 (1 << 5) -#define EXTI_FTSR1_FT6 (1 << 6) -#define EXTI_FTSR1_FT7 (1 << 7) -#define EXTI_FTSR1_FT8 (1 << 8) -#define EXTI_FTSR1_FT9 (1 << 9) -#define EXTI_FTSR1_FT10 (1 << 10) -#define EXTI_FTSR1_FT11 (1 << 11) -#define EXTI_FTSR1_FT12 (1 << 12) -#define EXTI_FTSR1_FT13 (1 << 13) -#define EXTI_FTSR1_FT14 (1 << 14) -#define EXTI_FTSR1_FT15 (1 << 15) -#define EXTI_FTSR1_FT16 (1 << 16) -#define EXTI_FTSR1_FT17 (1 << 17) -#define EXTI_FTSR1_FT18 (1 << 18) -#define EXTI_FTSR1_FT19 (1 << 19) -#define EXTI_FTSR1_FT20 (1 << 20) -#define EXTI_FTSR1_FT21 (1 << 21) -#define EXTI_FTSR1_FT22 (1 << 22) -#if STM32_EXTI_NLINES > 23 -#define EXTI_FTSR1_FT23 (1 << 23) -#endif -#if STM32_EXTI_NLINES > 24 -#define EXTI_FTSR1_FT24 (1 << 24) -#endif -#if STM32_EXTI_NLINES > 25 -#define EXTI_FTSR1_FT25 (1 << 25) -#endif - -/* EXTI software interrupt event register */ - -#define EXTI_SWIER1_SWI0 (1 << 0) -#define EXTI_SWIER1_SWI1 (1 << 1) -#define EXTI_SWIER1_SWI2 (1 << 2) -#define EXTI_SWIER1_SWI3 (1 << 3) -#define EXTI_SWIER1_SWI4 (1 << 4) -#define EXTI_SWIER1_SWI5 (1 << 5) -#define EXTI_SWIER1_SWI6 (1 << 6) -#define EXTI_SWIER1_SWI7 (1 << 7) -#define EXTI_SWIER1_SWI8 (1 << 8) -#define EXTI_SWIER1_SWI9 (1 << 9) -#define EXTI_SWIER1_SWI10 (1 << 10) -#define EXTI_SWIER1_SWI11 (1 << 11) -#define EXTI_SWIER1_SWI12 (1 << 12) -#define EXTI_SWIER1_SWI13 (1 << 13) -#define EXTI_SWIER1_SWI14 (1 << 14) -#define EXTI_SWIER1_SWI15 (1 << 15) -#define EXTI_SWIER1_SWI16 (1 << 16) -#define EXTI_SWIER1_SWI17 (1 << 17) -#define EXTI_SWIER1_SWI18 (1 << 18) -#define EXTI_SWIER1_SWI19 (1 << 19) -#define EXTI_SWIER1_SWI20 (1 << 20) -#define EXTI_SWIER1_SWI21 (1 << 21) -#define EXTI_SWIER1_SWI22 (1 << 22) -#if STM32_EXTI_NLINES > 23 -#define EXTI_SWIER1_SWI23 (1 << 23) -#endif -#if STM32_EXTI_NLINES > 24 -#define EXTI_SWIER1_SWI24 (1 << 24) -#endif -#if STM32_EXTI_NLINES > 25 -#define EXTI_SWIER1_SWI25 (1 << 25) -#endif - -/* EXTI rising edge pending register */ - -#define EXTI_RPR1_RPIF0 (1 << 0) -#define EXTI_RPR1_RPIF1 (1 << 1) -#define EXTI_RPR1_RPIF2 (1 << 2) -#define EXTI_RPR1_RPIF3 (1 << 3) -#define EXTI_RPR1_RPIF4 (1 << 4) -#define EXTI_RPR1_RPIF5 (1 << 5) -#define EXTI_RPR1_RPIF6 (1 << 6) -#define EXTI_RPR1_RPIF7 (1 << 7) -#define EXTI_RPR1_RPIF8 (1 << 8) -#define EXTI_RPR1_RPIF9 (1 << 9) -#define EXTI_RPR1_RPIF10 (1 << 10) -#define EXTI_RPR1_RPIF11 (1 << 11) -#define EXTI_RPR1_RPIF12 (1 << 12) -#define EXTI_RPR1_RPIF13 (1 << 13) -#define EXTI_RPR1_RPIF14 (1 << 14) -#define EXTI_RPR1_RPIF15 (1 << 15) -#define EXTI_RPR1_RPIF16 (1 << 16) -#define EXTI_RPR1_RPIF17 (1 << 17) -#define EXTI_RPR1_RPIF18 (1 << 18) -#define EXTI_RPR1_RPIF19 (1 << 19) -#define EXTI_RPR1_RPIF20 (1 << 20) -#define EXTI_RPR1_RPIF21 (1 << 21) -#define EXTI_RPR1_RPIF22 (1 << 22) -#if STM32_EXTI_NLINES > 23 -#define EXTI_RPR1_RPIF23 (1 << 23) -#endif -#if STM32_EXTI_NLINES > 24 -#define EXTI_RPR1_RPIF24 (1 << 24) -#endif -#if STM32_EXTI_NLINES > 25 -#define EXTI_RPR1_RPIF25 (1 << 25) -#endif - -/* EXTI falling edge pending register */ - -#define EXTI_FPR1_FPIF0 (1 << 0) -#define EXTI_FPR1_FPIF1 (1 << 1) -#define EXTI_FPR1_FPIF2 (1 << 2) -#define EXTI_FPR1_FPIF3 (1 << 3) -#define EXTI_FPR1_FPIF4 (1 << 4) -#define EXTI_FPR1_FPIF5 (1 << 5) -#define EXTI_FPR1_FPIF6 (1 << 6) -#define EXTI_FPR1_FPIF7 (1 << 7) -#define EXTI_FPR1_FPIF8 (1 << 8) -#define EXTI_FPR1_FPIF9 (1 << 9) -#define EXTI_FPR1_FPIF10 (1 << 10) -#define EXTI_FPR1_FPIF11 (1 << 11) -#define EXTI_FPR1_FPIF12 (1 << 12) -#define EXTI_FPR1_FPIF13 (1 << 13) -#define EXTI_FPR1_FPIF14 (1 << 14) -#define EXTI_FPR1_FPIF15 (1 << 15) -#define EXTI_FPR1_FPIF16 (1 << 16) -#define EXTI_FPR1_FPIF17 (1 << 17) -#define EXTI_FPR1_FPIF18 (1 << 18) -#define EXTI_FPR1_FPIF19 (1 << 19) -#define EXTI_FPR1_FPIF20 (1 << 20) -#define EXTI_FPR1_FPIF21 (1 << 21) -#define EXTI_FPR1_FPIF22 (1 << 22) -#if STM32_EXTI_NLINES > 23 -#define EXTI_FPR1_FPIF23 (1 << 23) -#endif -#if STM32_EXTI_NLINES > 24 -#define EXTI_FPR1_FPIF24 (1 << 24) -#endif -#if STM32_EXTI_NLINES > 25 -#define EXTI_FPR1_FPIF25 (1 << 25) -#endif - -/* EXTI security configuration register */ - -#define EXTI_SECCFGR1_SEC0 (1 << 0) -#define EXTI_SECCFGR1_SEC1 (1 << 1) -#define EXTI_SECCFGR1_SEC2 (1 << 2) -#define EXTI_SECCFGR1_SEC3 (1 << 3) -#define EXTI_SECCFGR1_SEC4 (1 << 4) -#define EXTI_SECCFGR1_SEC5 (1 << 5) -#define EXTI_SECCFGR1_SEC6 (1 << 6) -#define EXTI_SECCFGR1_SEC7 (1 << 7) -#define EXTI_SECCFGR1_SEC8 (1 << 8) -#define EXTI_SECCFGR1_SEC9 (1 << 9) -#define EXTI_SECCFGR1_SEC10 (1 << 10) -#define EXTI_SECCFGR1_SEC11 (1 << 11) -#define EXTI_SECCFGR1_SEC12 (1 << 12) -#define EXTI_SECCFGR1_SEC13 (1 << 13) -#define EXTI_SECCFGR1_SEC14 (1 << 14) -#define EXTI_SECCFGR1_SEC15 (1 << 15) -#define EXTI_SECCFGR1_SEC16 (1 << 16) -#define EXTI_SECCFGR1_SEC17 (1 << 17) -#define EXTI_SECCFGR1_SEC18 (1 << 18) -#define EXTI_SECCFGR1_SEC19 (1 << 19) -#define EXTI_SECCFGR1_SEC20 (1 << 20) -#define EXTI_SECCFGR1_SEC21 (1 << 21) -#define EXTI_SECCFGR1_SEC22 (1 << 22) -#if STM32_EXTI_NLINES > 23 -#define EXTI_SECCFGR1_SEC23 (1 << 23) -#endif -#if STM32_EXTI_NLINES > 24 -#define EXTI_SECCFGR1_SEC24 (1 << 24) -#endif -#if STM32_EXTI_NLINES > 25 -#define EXTI_SECCFGR1_SEC25 (1 << 25) -#endif - -/* EXTI privilege configuration register */ - -#define EXTI_PRIVCFGR1_PRIV0 (1 << 0) -#define EXTI_PRIVCFGR1_PRIV1 (1 << 1) -#define EXTI_PRIVCFGR1_PRIV2 (1 << 2) -#define EXTI_PRIVCFGR1_PRIV3 (1 << 3) -#define EXTI_PRIVCFGR1_PRIV4 (1 << 4) -#define EXTI_PRIVCFGR1_PRIV5 (1 << 5) -#define EXTI_PRIVCFGR1_PRIV6 (1 << 6) -#define EXTI_PRIVCFGR1_PRIV7 (1 << 7) -#define EXTI_PRIVCFGR1_PRIV8 (1 << 8) -#define EXTI_PRIVCFGR1_PRIV9 (1 << 9) -#define EXTI_PRIVCFGR1_PRIV10 (1 << 10) -#define EXTI_PRIVCFGR1_PRIV11 (1 << 11) -#define EXTI_PRIVCFGR1_PRIV12 (1 << 12) -#define EXTI_PRIVCFGR1_PRIV13 (1 << 13) -#define EXTI_PRIVCFGR1_PRIV14 (1 << 14) -#define EXTI_PRIVCFGR1_PRIV15 (1 << 15) -#define EXTI_PRIVCFGR1_PRIV16 (1 << 16) -#define EXTI_PRIVCFGR1_PRIV17 (1 << 17) -#define EXTI_PRIVCFGR1_PRIV18 (1 << 18) -#define EXTI_PRIVCFGR1_PRIV19 (1 << 19) -#define EXTI_PRIVCFGR1_PRIV20 (1 << 20) -#define EXTI_PRIVCFGR1_PRIV21 (1 << 21) -#define EXTI_PRIVCFGR1_PRIV22 (1 << 22) -#if STM32_EXTI_NLINES > 23 -#define EXTI_PRIVCFGR1_PRIV23 (1 << 23) -#endif -#if STM32_EXTI_NLINES > 24 -#define EXTI_PRIVCFGR1_PRIV24 (1 << 24) -#endif -#if STM32_EXTI_NLINES > 25 -#define EXTI_PRIVCFGR1_PRIV25 (1 << 25) -#endif - -/* EXTI external interrupt selection register */ - -#define EXTI_EXTICR1_EXTI0_SHIFT (0) -#define EXTI_EXTICR1_EXTI0_MASK (0xf << EXTI_EXTICR1_EXTI0_SHIFT) -#define EXTI_EXTICR1_EXTI0(n) ((n) << EXTI_EXTICR1_EXTI0_SHIFT) -#define EXTI_EXTICR1_EXTI1_SHIFT (8) -#define EXTI_EXTICR1_EXTI1_MASK (0xf << EXTI_EXTICR1_EXTI1_SHIFT) -#define EXTI_EXTICR1_EXTI1(n) ((n) << EXTI_EXTICR1_EXTI1_SHIFT) -#define EXTI_EXTICR1_EXTI2_SHIFT (16) -#define EXTI_EXTICR1_EXTI2_MASK (0xf << EXTI_EXTICR1_EXTI2_SHIFT) -#define EXTI_EXTICR1_EXTI2(n) ((n) << EXTI_EXTICR1_EXTI2_SHIFT) -#define EXTI_EXTICR1_EXTI3_SHIFT (24) -#define EXTI_EXTICR1_EXTI3_MASK (0xf << EXTI_EXTICR1_EXTI3_SHIFT) -#define EXTI_EXTICR1_EXTI3(n) ((n) << EXTI_EXTICR1_EXTI3_SHIFT) - -/* EXTI external interrupt selection register */ - -#define EXTI_EXTICR2_EXTI4_SHIFT (0) -#define EXTI_EXTICR2_EXTI4_MASK (0xf << EXTI_EXTICR2_EXTI4_SHIFT) -#define EXTI_EXTICR2_EXTI4(n) ((n) << EXTI_EXTICR2_EXTI4_SHIFT) -#define EXTI_EXTICR2_EXTI5_SHIFT (8) -#define EXTI_EXTICR2_EXTI5_MASK (0xf << EXTI_EXTICR2_EXTI5_SHIFT) -#define EXTI_EXTICR2_EXTI5(n) ((n) << EXTI_EXTICR2_EXTI5_SHIFT) -#define EXTI_EXTICR2_EXTI6_SHIFT (16) -#define EXTI_EXTICR2_EXTI6_MASK (0xf << EXTI_EXTICR2_EXTI6_SHIFT) -#define EXTI_EXTICR2_EXTI6(n) ((n) << EXTI_EXTICR2_EXTI6_SHIFT) -#define EXTI_EXTICR2_EXTI7_SHIFT (24) -#define EXTI_EXTICR2_EXTI7_MASK (0xf << EXTI_EXTICR2_EXTI7_SHIFT) -#define EXTI_EXTICR2_EXTI7(n) ((n) << EXTI_EXTICR2_EXTI7_SHIFT) - -/* EXTI external interrupt selection register */ - -#define EXTI_EXTICR3_EXTI8_SHIFT (0) -#define EXTI_EXTICR3_EXTI8_MASK (0xf << EXTI_EXTICR3_EXTI8_SHIFT) -#define EXTI_EXTICR3_EXTI8(n) ((n) << EXTI_EXTICR3_EXTI8_SHIFT) -#define EXTI_EXTICR3_EXTI9_SHIFT (8) -#define EXTI_EXTICR3_EXTI9_MASK (0xf << EXTI_EXTICR3_EXTI9_SHIFT) -#define EXTI_EXTICR3_EXTI9(n) ((n) << EXTI_EXTICR3_EXTI9_SHIFT) -#define EXTI_EXTICR3_EXTI10_SHIFT (16) -#define EXTI_EXTICR3_EXTI10_MASK (0xf << EXTI_EXTICR3_EXTI10_SHIFT) -#define EXTI_EXTICR3_EXTI10(n) ((n) << EXTI_EXTICR3_EXTI10_SHIFT) -#define EXTI_EXTICR3_EXTI11_SHIFT (24) -#define EXTI_EXTICR3_EXTI11_MASK (0xf << EXTI_EXTICR3_EXTI11_SHIFT) -#define EXTI_EXTICR3_EXTI11(n) ((n) << EXTI_EXTICR3_EXTI11_SHIFT) - -/* EXTI external interrupt selection register */ - -#define EXTI_EXTICR4_EXTI12_SHIFT (0) -#define EXTI_EXTICR4_EXTI12_MASK (0xf << EXTI_EXTICR4_EXTI12_SHIFT) -#define EXTI_EXTICR4_EXTI12(n) ((n) << EXTI_EXTICR4_EXTI12_SHIFT) -#define EXTI_EXTICR4_EXTI13_SHIFT (8) -#define EXTI_EXTICR4_EXTI13_MASK (0xf << EXTI_EXTICR4_EXTI13_SHIFT) -#define EXTI_EXTICR4_EXTI13(n) ((n) << EXTI_EXTICR4_EXTI13_SHIFT) -#define EXTI_EXTICR4_EXTI14_SHIFT (16) -#define EXTI_EXTICR4_EXTI14_MASK (0xf << EXTI_EXTICR4_EXTI14_SHIFT) -#define EXTI_EXTICR4_EXTI14(n) ((n) << EXTI_EXTICR4_EXTI14_SHIFT) -#define EXTI_EXTICR4_EXTI15_SHIFT (24) -#define EXTI_EXTICR4_EXTI15_MASK (0xf << EXTI_EXTICR4_EXTI15_SHIFT) -#define EXTI_EXTICR4_EXTI15(n) ((n) << EXTI_EXTICR4_EXTI15_SHIFT) +/* Each implemented EXTI line occupies one bit in its register bank. Lines + * 0-31 use bank 1 and lines 32-63 use bank 2. Use only lines implemented in + * the selected register; trigger/pending and mask registers can differ. + */ + +#define STM32_EXTI_BIT(n) (1u << ((n) & 31)) + +/* EXTI rising trigger selection register 1 */ + +#define EXTI_RTSR1_RT0 STM32_EXTI_BIT(0) +#define EXTI_RTSR1_RT1 STM32_EXTI_BIT(1) +#define EXTI_RTSR1_RT2 STM32_EXTI_BIT(2) +#define EXTI_RTSR1_RT3 STM32_EXTI_BIT(3) +#define EXTI_RTSR1_RT4 STM32_EXTI_BIT(4) +#define EXTI_RTSR1_RT5 STM32_EXTI_BIT(5) +#define EXTI_RTSR1_RT6 STM32_EXTI_BIT(6) +#define EXTI_RTSR1_RT7 STM32_EXTI_BIT(7) +#define EXTI_RTSR1_RT8 STM32_EXTI_BIT(8) +#define EXTI_RTSR1_RT9 STM32_EXTI_BIT(9) +#define EXTI_RTSR1_RT10 STM32_EXTI_BIT(10) +#define EXTI_RTSR1_RT11 STM32_EXTI_BIT(11) +#define EXTI_RTSR1_RT12 STM32_EXTI_BIT(12) +#define EXTI_RTSR1_RT13 STM32_EXTI_BIT(13) +#define EXTI_RTSR1_RT14 STM32_EXTI_BIT(14) +#define EXTI_RTSR1_RT15 STM32_EXTI_BIT(15) +#define EXTI_RTSR1_RT16 STM32_EXTI_BIT(16) +#define EXTI_RTSR1_RT17 STM32_EXTI_BIT(17) +#define EXTI_RTSR1_RT18 STM32_EXTI_BIT(18) +#define EXTI_RTSR1_RT19 STM32_EXTI_BIT(19) +#define EXTI_RTSR1_RT20 STM32_EXTI_BIT(20) +#define EXTI_RTSR1_RT21 STM32_EXTI_BIT(21) +#define EXTI_RTSR1_RT22 STM32_EXTI_BIT(22) +#define EXTI_RTSR1_RT23 STM32_EXTI_BIT(23) +#define EXTI_RTSR1_RT24 STM32_EXTI_BIT(24) +#define EXTI_RTSR1_RT25 STM32_EXTI_BIT(25) +#define EXTI_RTSR1_RT26 STM32_EXTI_BIT(26) +#define EXTI_RTSR1_RT27 STM32_EXTI_BIT(27) +#define EXTI_RTSR1_RT28 STM32_EXTI_BIT(28) +#define EXTI_RTSR1_RT29 STM32_EXTI_BIT(29) +#define EXTI_RTSR1_RT30 STM32_EXTI_BIT(30) +#define EXTI_RTSR1_RT31 STM32_EXTI_BIT(31) + +/* EXTI rising trigger selection register 2 */ + +#define EXTI_RTSR2_RT32 STM32_EXTI_BIT(32) +#define EXTI_RTSR2_RT33 STM32_EXTI_BIT(33) +#define EXTI_RTSR2_RT34 STM32_EXTI_BIT(34) +#define EXTI_RTSR2_RT35 STM32_EXTI_BIT(35) +#define EXTI_RTSR2_RT36 STM32_EXTI_BIT(36) +#define EXTI_RTSR2_RT37 STM32_EXTI_BIT(37) +#define EXTI_RTSR2_RT38 STM32_EXTI_BIT(38) +#define EXTI_RTSR2_RT39 STM32_EXTI_BIT(39) +#define EXTI_RTSR2_RT40 STM32_EXTI_BIT(40) +#define EXTI_RTSR2_RT41 STM32_EXTI_BIT(41) +#define EXTI_RTSR2_RT42 STM32_EXTI_BIT(42) +#define EXTI_RTSR2_RT43 STM32_EXTI_BIT(43) +#define EXTI_RTSR2_RT44 STM32_EXTI_BIT(44) +#define EXTI_RTSR2_RT45 STM32_EXTI_BIT(45) +#define EXTI_RTSR2_RT46 STM32_EXTI_BIT(46) +#define EXTI_RTSR2_RT47 STM32_EXTI_BIT(47) +#define EXTI_RTSR2_RT48 STM32_EXTI_BIT(48) +#define EXTI_RTSR2_RT49 STM32_EXTI_BIT(49) +#define EXTI_RTSR2_RT50 STM32_EXTI_BIT(50) +#define EXTI_RTSR2_RT51 STM32_EXTI_BIT(51) +#define EXTI_RTSR2_RT52 STM32_EXTI_BIT(52) +#define EXTI_RTSR2_RT53 STM32_EXTI_BIT(53) +#define EXTI_RTSR2_RT54 STM32_EXTI_BIT(54) +#define EXTI_RTSR2_RT55 STM32_EXTI_BIT(55) +#define EXTI_RTSR2_RT56 STM32_EXTI_BIT(56) +#define EXTI_RTSR2_RT57 STM32_EXTI_BIT(57) +#define EXTI_RTSR2_RT58 STM32_EXTI_BIT(58) +#define EXTI_RTSR2_RT59 STM32_EXTI_BIT(59) +#define EXTI_RTSR2_RT60 STM32_EXTI_BIT(60) +#define EXTI_RTSR2_RT61 STM32_EXTI_BIT(61) +#define EXTI_RTSR2_RT62 STM32_EXTI_BIT(62) +#define EXTI_RTSR2_RT63 STM32_EXTI_BIT(63) + +/* EXTI falling trigger selection register 1 */ + +#define EXTI_FTSR1_FT0 STM32_EXTI_BIT(0) +#define EXTI_FTSR1_FT1 STM32_EXTI_BIT(1) +#define EXTI_FTSR1_FT2 STM32_EXTI_BIT(2) +#define EXTI_FTSR1_FT3 STM32_EXTI_BIT(3) +#define EXTI_FTSR1_FT4 STM32_EXTI_BIT(4) +#define EXTI_FTSR1_FT5 STM32_EXTI_BIT(5) +#define EXTI_FTSR1_FT6 STM32_EXTI_BIT(6) +#define EXTI_FTSR1_FT7 STM32_EXTI_BIT(7) +#define EXTI_FTSR1_FT8 STM32_EXTI_BIT(8) +#define EXTI_FTSR1_FT9 STM32_EXTI_BIT(9) +#define EXTI_FTSR1_FT10 STM32_EXTI_BIT(10) +#define EXTI_FTSR1_FT11 STM32_EXTI_BIT(11) +#define EXTI_FTSR1_FT12 STM32_EXTI_BIT(12) +#define EXTI_FTSR1_FT13 STM32_EXTI_BIT(13) +#define EXTI_FTSR1_FT14 STM32_EXTI_BIT(14) +#define EXTI_FTSR1_FT15 STM32_EXTI_BIT(15) +#define EXTI_FTSR1_FT16 STM32_EXTI_BIT(16) +#define EXTI_FTSR1_FT17 STM32_EXTI_BIT(17) +#define EXTI_FTSR1_FT18 STM32_EXTI_BIT(18) +#define EXTI_FTSR1_FT19 STM32_EXTI_BIT(19) +#define EXTI_FTSR1_FT20 STM32_EXTI_BIT(20) +#define EXTI_FTSR1_FT21 STM32_EXTI_BIT(21) +#define EXTI_FTSR1_FT22 STM32_EXTI_BIT(22) +#define EXTI_FTSR1_FT23 STM32_EXTI_BIT(23) +#define EXTI_FTSR1_FT24 STM32_EXTI_BIT(24) +#define EXTI_FTSR1_FT25 STM32_EXTI_BIT(25) +#define EXTI_FTSR1_FT26 STM32_EXTI_BIT(26) +#define EXTI_FTSR1_FT27 STM32_EXTI_BIT(27) +#define EXTI_FTSR1_FT28 STM32_EXTI_BIT(28) +#define EXTI_FTSR1_FT29 STM32_EXTI_BIT(29) +#define EXTI_FTSR1_FT30 STM32_EXTI_BIT(30) +#define EXTI_FTSR1_FT31 STM32_EXTI_BIT(31) + +/* EXTI falling trigger selection register 2 */ + +#define EXTI_FTSR2_FT32 STM32_EXTI_BIT(32) +#define EXTI_FTSR2_FT33 STM32_EXTI_BIT(33) +#define EXTI_FTSR2_FT34 STM32_EXTI_BIT(34) +#define EXTI_FTSR2_FT35 STM32_EXTI_BIT(35) +#define EXTI_FTSR2_FT36 STM32_EXTI_BIT(36) +#define EXTI_FTSR2_FT37 STM32_EXTI_BIT(37) +#define EXTI_FTSR2_FT38 STM32_EXTI_BIT(38) +#define EXTI_FTSR2_FT39 STM32_EXTI_BIT(39) +#define EXTI_FTSR2_FT40 STM32_EXTI_BIT(40) +#define EXTI_FTSR2_FT41 STM32_EXTI_BIT(41) +#define EXTI_FTSR2_FT42 STM32_EXTI_BIT(42) +#define EXTI_FTSR2_FT43 STM32_EXTI_BIT(43) +#define EXTI_FTSR2_FT44 STM32_EXTI_BIT(44) +#define EXTI_FTSR2_FT45 STM32_EXTI_BIT(45) +#define EXTI_FTSR2_FT46 STM32_EXTI_BIT(46) +#define EXTI_FTSR2_FT47 STM32_EXTI_BIT(47) +#define EXTI_FTSR2_FT48 STM32_EXTI_BIT(48) +#define EXTI_FTSR2_FT49 STM32_EXTI_BIT(49) +#define EXTI_FTSR2_FT50 STM32_EXTI_BIT(50) +#define EXTI_FTSR2_FT51 STM32_EXTI_BIT(51) +#define EXTI_FTSR2_FT52 STM32_EXTI_BIT(52) +#define EXTI_FTSR2_FT53 STM32_EXTI_BIT(53) +#define EXTI_FTSR2_FT54 STM32_EXTI_BIT(54) +#define EXTI_FTSR2_FT55 STM32_EXTI_BIT(55) +#define EXTI_FTSR2_FT56 STM32_EXTI_BIT(56) +#define EXTI_FTSR2_FT57 STM32_EXTI_BIT(57) +#define EXTI_FTSR2_FT58 STM32_EXTI_BIT(58) +#define EXTI_FTSR2_FT59 STM32_EXTI_BIT(59) +#define EXTI_FTSR2_FT60 STM32_EXTI_BIT(60) +#define EXTI_FTSR2_FT61 STM32_EXTI_BIT(61) +#define EXTI_FTSR2_FT62 STM32_EXTI_BIT(62) +#define EXTI_FTSR2_FT63 STM32_EXTI_BIT(63) + +/* EXTI software interrupt event register 1 */ + +#define EXTI_SWIER1_SWI0 STM32_EXTI_BIT(0) +#define EXTI_SWIER1_SWI1 STM32_EXTI_BIT(1) +#define EXTI_SWIER1_SWI2 STM32_EXTI_BIT(2) +#define EXTI_SWIER1_SWI3 STM32_EXTI_BIT(3) +#define EXTI_SWIER1_SWI4 STM32_EXTI_BIT(4) +#define EXTI_SWIER1_SWI5 STM32_EXTI_BIT(5) +#define EXTI_SWIER1_SWI6 STM32_EXTI_BIT(6) +#define EXTI_SWIER1_SWI7 STM32_EXTI_BIT(7) +#define EXTI_SWIER1_SWI8 STM32_EXTI_BIT(8) +#define EXTI_SWIER1_SWI9 STM32_EXTI_BIT(9) +#define EXTI_SWIER1_SWI10 STM32_EXTI_BIT(10) +#define EXTI_SWIER1_SWI11 STM32_EXTI_BIT(11) +#define EXTI_SWIER1_SWI12 STM32_EXTI_BIT(12) +#define EXTI_SWIER1_SWI13 STM32_EXTI_BIT(13) +#define EXTI_SWIER1_SWI14 STM32_EXTI_BIT(14) +#define EXTI_SWIER1_SWI15 STM32_EXTI_BIT(15) +#define EXTI_SWIER1_SWI16 STM32_EXTI_BIT(16) +#define EXTI_SWIER1_SWI17 STM32_EXTI_BIT(17) +#define EXTI_SWIER1_SWI18 STM32_EXTI_BIT(18) +#define EXTI_SWIER1_SWI19 STM32_EXTI_BIT(19) +#define EXTI_SWIER1_SWI20 STM32_EXTI_BIT(20) +#define EXTI_SWIER1_SWI21 STM32_EXTI_BIT(21) +#define EXTI_SWIER1_SWI22 STM32_EXTI_BIT(22) +#define EXTI_SWIER1_SWI23 STM32_EXTI_BIT(23) +#define EXTI_SWIER1_SWI24 STM32_EXTI_BIT(24) +#define EXTI_SWIER1_SWI25 STM32_EXTI_BIT(25) +#define EXTI_SWIER1_SWI26 STM32_EXTI_BIT(26) +#define EXTI_SWIER1_SWI27 STM32_EXTI_BIT(27) +#define EXTI_SWIER1_SWI28 STM32_EXTI_BIT(28) +#define EXTI_SWIER1_SWI29 STM32_EXTI_BIT(29) +#define EXTI_SWIER1_SWI30 STM32_EXTI_BIT(30) +#define EXTI_SWIER1_SWI31 STM32_EXTI_BIT(31) + +/* EXTI software interrupt event register 2 */ + +#define EXTI_SWIER2_SWI32 STM32_EXTI_BIT(32) +#define EXTI_SWIER2_SWI33 STM32_EXTI_BIT(33) +#define EXTI_SWIER2_SWI34 STM32_EXTI_BIT(34) +#define EXTI_SWIER2_SWI35 STM32_EXTI_BIT(35) +#define EXTI_SWIER2_SWI36 STM32_EXTI_BIT(36) +#define EXTI_SWIER2_SWI37 STM32_EXTI_BIT(37) +#define EXTI_SWIER2_SWI38 STM32_EXTI_BIT(38) +#define EXTI_SWIER2_SWI39 STM32_EXTI_BIT(39) +#define EXTI_SWIER2_SWI40 STM32_EXTI_BIT(40) +#define EXTI_SWIER2_SWI41 STM32_EXTI_BIT(41) +#define EXTI_SWIER2_SWI42 STM32_EXTI_BIT(42) +#define EXTI_SWIER2_SWI43 STM32_EXTI_BIT(43) +#define EXTI_SWIER2_SWI44 STM32_EXTI_BIT(44) +#define EXTI_SWIER2_SWI45 STM32_EXTI_BIT(45) +#define EXTI_SWIER2_SWI46 STM32_EXTI_BIT(46) +#define EXTI_SWIER2_SWI47 STM32_EXTI_BIT(47) +#define EXTI_SWIER2_SWI48 STM32_EXTI_BIT(48) +#define EXTI_SWIER2_SWI49 STM32_EXTI_BIT(49) +#define EXTI_SWIER2_SWI50 STM32_EXTI_BIT(50) +#define EXTI_SWIER2_SWI51 STM32_EXTI_BIT(51) +#define EXTI_SWIER2_SWI52 STM32_EXTI_BIT(52) +#define EXTI_SWIER2_SWI53 STM32_EXTI_BIT(53) +#define EXTI_SWIER2_SWI54 STM32_EXTI_BIT(54) +#define EXTI_SWIER2_SWI55 STM32_EXTI_BIT(55) +#define EXTI_SWIER2_SWI56 STM32_EXTI_BIT(56) +#define EXTI_SWIER2_SWI57 STM32_EXTI_BIT(57) +#define EXTI_SWIER2_SWI58 STM32_EXTI_BIT(58) +#define EXTI_SWIER2_SWI59 STM32_EXTI_BIT(59) +#define EXTI_SWIER2_SWI60 STM32_EXTI_BIT(60) +#define EXTI_SWIER2_SWI61 STM32_EXTI_BIT(61) +#define EXTI_SWIER2_SWI62 STM32_EXTI_BIT(62) +#define EXTI_SWIER2_SWI63 STM32_EXTI_BIT(63) + +/* EXTI rising edge pending register 1 */ + +#define EXTI_RPR1_RPIF0 STM32_EXTI_BIT(0) +#define EXTI_RPR1_RPIF1 STM32_EXTI_BIT(1) +#define EXTI_RPR1_RPIF2 STM32_EXTI_BIT(2) +#define EXTI_RPR1_RPIF3 STM32_EXTI_BIT(3) +#define EXTI_RPR1_RPIF4 STM32_EXTI_BIT(4) +#define EXTI_RPR1_RPIF5 STM32_EXTI_BIT(5) +#define EXTI_RPR1_RPIF6 STM32_EXTI_BIT(6) +#define EXTI_RPR1_RPIF7 STM32_EXTI_BIT(7) +#define EXTI_RPR1_RPIF8 STM32_EXTI_BIT(8) +#define EXTI_RPR1_RPIF9 STM32_EXTI_BIT(9) +#define EXTI_RPR1_RPIF10 STM32_EXTI_BIT(10) +#define EXTI_RPR1_RPIF11 STM32_EXTI_BIT(11) +#define EXTI_RPR1_RPIF12 STM32_EXTI_BIT(12) +#define EXTI_RPR1_RPIF13 STM32_EXTI_BIT(13) +#define EXTI_RPR1_RPIF14 STM32_EXTI_BIT(14) +#define EXTI_RPR1_RPIF15 STM32_EXTI_BIT(15) +#define EXTI_RPR1_RPIF16 STM32_EXTI_BIT(16) +#define EXTI_RPR1_RPIF17 STM32_EXTI_BIT(17) +#define EXTI_RPR1_RPIF18 STM32_EXTI_BIT(18) +#define EXTI_RPR1_RPIF19 STM32_EXTI_BIT(19) +#define EXTI_RPR1_RPIF20 STM32_EXTI_BIT(20) +#define EXTI_RPR1_RPIF21 STM32_EXTI_BIT(21) +#define EXTI_RPR1_RPIF22 STM32_EXTI_BIT(22) +#define EXTI_RPR1_RPIF23 STM32_EXTI_BIT(23) +#define EXTI_RPR1_RPIF24 STM32_EXTI_BIT(24) +#define EXTI_RPR1_RPIF25 STM32_EXTI_BIT(25) +#define EXTI_RPR1_RPIF26 STM32_EXTI_BIT(26) +#define EXTI_RPR1_RPIF27 STM32_EXTI_BIT(27) +#define EXTI_RPR1_RPIF28 STM32_EXTI_BIT(28) +#define EXTI_RPR1_RPIF29 STM32_EXTI_BIT(29) +#define EXTI_RPR1_RPIF30 STM32_EXTI_BIT(30) +#define EXTI_RPR1_RPIF31 STM32_EXTI_BIT(31) + +/* EXTI rising edge pending register 2 */ + +#define EXTI_RPR2_RPIF32 STM32_EXTI_BIT(32) +#define EXTI_RPR2_RPIF33 STM32_EXTI_BIT(33) +#define EXTI_RPR2_RPIF34 STM32_EXTI_BIT(34) +#define EXTI_RPR2_RPIF35 STM32_EXTI_BIT(35) +#define EXTI_RPR2_RPIF36 STM32_EXTI_BIT(36) +#define EXTI_RPR2_RPIF37 STM32_EXTI_BIT(37) +#define EXTI_RPR2_RPIF38 STM32_EXTI_BIT(38) +#define EXTI_RPR2_RPIF39 STM32_EXTI_BIT(39) +#define EXTI_RPR2_RPIF40 STM32_EXTI_BIT(40) +#define EXTI_RPR2_RPIF41 STM32_EXTI_BIT(41) +#define EXTI_RPR2_RPIF42 STM32_EXTI_BIT(42) +#define EXTI_RPR2_RPIF43 STM32_EXTI_BIT(43) +#define EXTI_RPR2_RPIF44 STM32_EXTI_BIT(44) +#define EXTI_RPR2_RPIF45 STM32_EXTI_BIT(45) +#define EXTI_RPR2_RPIF46 STM32_EXTI_BIT(46) +#define EXTI_RPR2_RPIF47 STM32_EXTI_BIT(47) +#define EXTI_RPR2_RPIF48 STM32_EXTI_BIT(48) +#define EXTI_RPR2_RPIF49 STM32_EXTI_BIT(49) +#define EXTI_RPR2_RPIF50 STM32_EXTI_BIT(50) +#define EXTI_RPR2_RPIF51 STM32_EXTI_BIT(51) +#define EXTI_RPR2_RPIF52 STM32_EXTI_BIT(52) +#define EXTI_RPR2_RPIF53 STM32_EXTI_BIT(53) +#define EXTI_RPR2_RPIF54 STM32_EXTI_BIT(54) +#define EXTI_RPR2_RPIF55 STM32_EXTI_BIT(55) +#define EXTI_RPR2_RPIF56 STM32_EXTI_BIT(56) +#define EXTI_RPR2_RPIF57 STM32_EXTI_BIT(57) +#define EXTI_RPR2_RPIF58 STM32_EXTI_BIT(58) +#define EXTI_RPR2_RPIF59 STM32_EXTI_BIT(59) +#define EXTI_RPR2_RPIF60 STM32_EXTI_BIT(60) +#define EXTI_RPR2_RPIF61 STM32_EXTI_BIT(61) +#define EXTI_RPR2_RPIF62 STM32_EXTI_BIT(62) +#define EXTI_RPR2_RPIF63 STM32_EXTI_BIT(63) + +/* EXTI falling edge pending register 1 */ + +#define EXTI_FPR1_FPIF0 STM32_EXTI_BIT(0) +#define EXTI_FPR1_FPIF1 STM32_EXTI_BIT(1) +#define EXTI_FPR1_FPIF2 STM32_EXTI_BIT(2) +#define EXTI_FPR1_FPIF3 STM32_EXTI_BIT(3) +#define EXTI_FPR1_FPIF4 STM32_EXTI_BIT(4) +#define EXTI_FPR1_FPIF5 STM32_EXTI_BIT(5) +#define EXTI_FPR1_FPIF6 STM32_EXTI_BIT(6) +#define EXTI_FPR1_FPIF7 STM32_EXTI_BIT(7) +#define EXTI_FPR1_FPIF8 STM32_EXTI_BIT(8) +#define EXTI_FPR1_FPIF9 STM32_EXTI_BIT(9) +#define EXTI_FPR1_FPIF10 STM32_EXTI_BIT(10) +#define EXTI_FPR1_FPIF11 STM32_EXTI_BIT(11) +#define EXTI_FPR1_FPIF12 STM32_EXTI_BIT(12) +#define EXTI_FPR1_FPIF13 STM32_EXTI_BIT(13) +#define EXTI_FPR1_FPIF14 STM32_EXTI_BIT(14) +#define EXTI_FPR1_FPIF15 STM32_EXTI_BIT(15) +#define EXTI_FPR1_FPIF16 STM32_EXTI_BIT(16) +#define EXTI_FPR1_FPIF17 STM32_EXTI_BIT(17) +#define EXTI_FPR1_FPIF18 STM32_EXTI_BIT(18) +#define EXTI_FPR1_FPIF19 STM32_EXTI_BIT(19) +#define EXTI_FPR1_FPIF20 STM32_EXTI_BIT(20) +#define EXTI_FPR1_FPIF21 STM32_EXTI_BIT(21) +#define EXTI_FPR1_FPIF22 STM32_EXTI_BIT(22) +#define EXTI_FPR1_FPIF23 STM32_EXTI_BIT(23) +#define EXTI_FPR1_FPIF24 STM32_EXTI_BIT(24) +#define EXTI_FPR1_FPIF25 STM32_EXTI_BIT(25) +#define EXTI_FPR1_FPIF26 STM32_EXTI_BIT(26) +#define EXTI_FPR1_FPIF27 STM32_EXTI_BIT(27) +#define EXTI_FPR1_FPIF28 STM32_EXTI_BIT(28) +#define EXTI_FPR1_FPIF29 STM32_EXTI_BIT(29) +#define EXTI_FPR1_FPIF30 STM32_EXTI_BIT(30) +#define EXTI_FPR1_FPIF31 STM32_EXTI_BIT(31) + +/* EXTI falling edge pending register 2 */ + +#define EXTI_FPR2_FPIF32 STM32_EXTI_BIT(32) +#define EXTI_FPR2_FPIF33 STM32_EXTI_BIT(33) +#define EXTI_FPR2_FPIF34 STM32_EXTI_BIT(34) +#define EXTI_FPR2_FPIF35 STM32_EXTI_BIT(35) +#define EXTI_FPR2_FPIF36 STM32_EXTI_BIT(36) +#define EXTI_FPR2_FPIF37 STM32_EXTI_BIT(37) +#define EXTI_FPR2_FPIF38 STM32_EXTI_BIT(38) +#define EXTI_FPR2_FPIF39 STM32_EXTI_BIT(39) +#define EXTI_FPR2_FPIF40 STM32_EXTI_BIT(40) +#define EXTI_FPR2_FPIF41 STM32_EXTI_BIT(41) +#define EXTI_FPR2_FPIF42 STM32_EXTI_BIT(42) +#define EXTI_FPR2_FPIF43 STM32_EXTI_BIT(43) +#define EXTI_FPR2_FPIF44 STM32_EXTI_BIT(44) +#define EXTI_FPR2_FPIF45 STM32_EXTI_BIT(45) +#define EXTI_FPR2_FPIF46 STM32_EXTI_BIT(46) +#define EXTI_FPR2_FPIF47 STM32_EXTI_BIT(47) +#define EXTI_FPR2_FPIF48 STM32_EXTI_BIT(48) +#define EXTI_FPR2_FPIF49 STM32_EXTI_BIT(49) +#define EXTI_FPR2_FPIF50 STM32_EXTI_BIT(50) +#define EXTI_FPR2_FPIF51 STM32_EXTI_BIT(51) +#define EXTI_FPR2_FPIF52 STM32_EXTI_BIT(52) +#define EXTI_FPR2_FPIF53 STM32_EXTI_BIT(53) +#define EXTI_FPR2_FPIF54 STM32_EXTI_BIT(54) +#define EXTI_FPR2_FPIF55 STM32_EXTI_BIT(55) +#define EXTI_FPR2_FPIF56 STM32_EXTI_BIT(56) +#define EXTI_FPR2_FPIF57 STM32_EXTI_BIT(57) +#define EXTI_FPR2_FPIF58 STM32_EXTI_BIT(58) +#define EXTI_FPR2_FPIF59 STM32_EXTI_BIT(59) +#define EXTI_FPR2_FPIF60 STM32_EXTI_BIT(60) +#define EXTI_FPR2_FPIF61 STM32_EXTI_BIT(61) +#define EXTI_FPR2_FPIF62 STM32_EXTI_BIT(62) +#define EXTI_FPR2_FPIF63 STM32_EXTI_BIT(63) + +/* EXTI security configuration register 1 */ + +#define EXTI_SECCFGR1_SEC0 STM32_EXTI_BIT(0) +#define EXTI_SECCFGR1_SEC1 STM32_EXTI_BIT(1) +#define EXTI_SECCFGR1_SEC2 STM32_EXTI_BIT(2) +#define EXTI_SECCFGR1_SEC3 STM32_EXTI_BIT(3) +#define EXTI_SECCFGR1_SEC4 STM32_EXTI_BIT(4) +#define EXTI_SECCFGR1_SEC5 STM32_EXTI_BIT(5) +#define EXTI_SECCFGR1_SEC6 STM32_EXTI_BIT(6) +#define EXTI_SECCFGR1_SEC7 STM32_EXTI_BIT(7) +#define EXTI_SECCFGR1_SEC8 STM32_EXTI_BIT(8) +#define EXTI_SECCFGR1_SEC9 STM32_EXTI_BIT(9) +#define EXTI_SECCFGR1_SEC10 STM32_EXTI_BIT(10) +#define EXTI_SECCFGR1_SEC11 STM32_EXTI_BIT(11) +#define EXTI_SECCFGR1_SEC12 STM32_EXTI_BIT(12) +#define EXTI_SECCFGR1_SEC13 STM32_EXTI_BIT(13) +#define EXTI_SECCFGR1_SEC14 STM32_EXTI_BIT(14) +#define EXTI_SECCFGR1_SEC15 STM32_EXTI_BIT(15) +#define EXTI_SECCFGR1_SEC16 STM32_EXTI_BIT(16) +#define EXTI_SECCFGR1_SEC17 STM32_EXTI_BIT(17) +#define EXTI_SECCFGR1_SEC18 STM32_EXTI_BIT(18) +#define EXTI_SECCFGR1_SEC19 STM32_EXTI_BIT(19) +#define EXTI_SECCFGR1_SEC20 STM32_EXTI_BIT(20) +#define EXTI_SECCFGR1_SEC21 STM32_EXTI_BIT(21) +#define EXTI_SECCFGR1_SEC22 STM32_EXTI_BIT(22) +#define EXTI_SECCFGR1_SEC23 STM32_EXTI_BIT(23) +#define EXTI_SECCFGR1_SEC24 STM32_EXTI_BIT(24) +#define EXTI_SECCFGR1_SEC25 STM32_EXTI_BIT(25) +#define EXTI_SECCFGR1_SEC26 STM32_EXTI_BIT(26) +#define EXTI_SECCFGR1_SEC27 STM32_EXTI_BIT(27) +#define EXTI_SECCFGR1_SEC28 STM32_EXTI_BIT(28) +#define EXTI_SECCFGR1_SEC29 STM32_EXTI_BIT(29) +#define EXTI_SECCFGR1_SEC30 STM32_EXTI_BIT(30) +#define EXTI_SECCFGR1_SEC31 STM32_EXTI_BIT(31) + +/* EXTI security configuration register 2 */ + +#define EXTI_SECCFGR2_SEC32 STM32_EXTI_BIT(32) +#define EXTI_SECCFGR2_SEC33 STM32_EXTI_BIT(33) +#define EXTI_SECCFGR2_SEC34 STM32_EXTI_BIT(34) +#define EXTI_SECCFGR2_SEC35 STM32_EXTI_BIT(35) +#define EXTI_SECCFGR2_SEC36 STM32_EXTI_BIT(36) +#define EXTI_SECCFGR2_SEC37 STM32_EXTI_BIT(37) +#define EXTI_SECCFGR2_SEC38 STM32_EXTI_BIT(38) +#define EXTI_SECCFGR2_SEC39 STM32_EXTI_BIT(39) +#define EXTI_SECCFGR2_SEC40 STM32_EXTI_BIT(40) +#define EXTI_SECCFGR2_SEC41 STM32_EXTI_BIT(41) +#define EXTI_SECCFGR2_SEC42 STM32_EXTI_BIT(42) +#define EXTI_SECCFGR2_SEC43 STM32_EXTI_BIT(43) +#define EXTI_SECCFGR2_SEC44 STM32_EXTI_BIT(44) +#define EXTI_SECCFGR2_SEC45 STM32_EXTI_BIT(45) +#define EXTI_SECCFGR2_SEC46 STM32_EXTI_BIT(46) +#define EXTI_SECCFGR2_SEC47 STM32_EXTI_BIT(47) +#define EXTI_SECCFGR2_SEC48 STM32_EXTI_BIT(48) +#define EXTI_SECCFGR2_SEC49 STM32_EXTI_BIT(49) +#define EXTI_SECCFGR2_SEC50 STM32_EXTI_BIT(50) +#define EXTI_SECCFGR2_SEC51 STM32_EXTI_BIT(51) +#define EXTI_SECCFGR2_SEC52 STM32_EXTI_BIT(52) +#define EXTI_SECCFGR2_SEC53 STM32_EXTI_BIT(53) +#define EXTI_SECCFGR2_SEC54 STM32_EXTI_BIT(54) +#define EXTI_SECCFGR2_SEC55 STM32_EXTI_BIT(55) +#define EXTI_SECCFGR2_SEC56 STM32_EXTI_BIT(56) +#define EXTI_SECCFGR2_SEC57 STM32_EXTI_BIT(57) +#define EXTI_SECCFGR2_SEC58 STM32_EXTI_BIT(58) +#define EXTI_SECCFGR2_SEC59 STM32_EXTI_BIT(59) +#define EXTI_SECCFGR2_SEC60 STM32_EXTI_BIT(60) +#define EXTI_SECCFGR2_SEC61 STM32_EXTI_BIT(61) +#define EXTI_SECCFGR2_SEC62 STM32_EXTI_BIT(62) +#define EXTI_SECCFGR2_SEC63 STM32_EXTI_BIT(63) + +/* EXTI privilege configuration register 1 */ + +#define EXTI_PRIVCFGR1_PRIV0 STM32_EXTI_BIT(0) +#define EXTI_PRIVCFGR1_PRIV1 STM32_EXTI_BIT(1) +#define EXTI_PRIVCFGR1_PRIV2 STM32_EXTI_BIT(2) +#define EXTI_PRIVCFGR1_PRIV3 STM32_EXTI_BIT(3) +#define EXTI_PRIVCFGR1_PRIV4 STM32_EXTI_BIT(4) +#define EXTI_PRIVCFGR1_PRIV5 STM32_EXTI_BIT(5) +#define EXTI_PRIVCFGR1_PRIV6 STM32_EXTI_BIT(6) +#define EXTI_PRIVCFGR1_PRIV7 STM32_EXTI_BIT(7) +#define EXTI_PRIVCFGR1_PRIV8 STM32_EXTI_BIT(8) +#define EXTI_PRIVCFGR1_PRIV9 STM32_EXTI_BIT(9) +#define EXTI_PRIVCFGR1_PRIV10 STM32_EXTI_BIT(10) +#define EXTI_PRIVCFGR1_PRIV11 STM32_EXTI_BIT(11) +#define EXTI_PRIVCFGR1_PRIV12 STM32_EXTI_BIT(12) +#define EXTI_PRIVCFGR1_PRIV13 STM32_EXTI_BIT(13) +#define EXTI_PRIVCFGR1_PRIV14 STM32_EXTI_BIT(14) +#define EXTI_PRIVCFGR1_PRIV15 STM32_EXTI_BIT(15) +#define EXTI_PRIVCFGR1_PRIV16 STM32_EXTI_BIT(16) +#define EXTI_PRIVCFGR1_PRIV17 STM32_EXTI_BIT(17) +#define EXTI_PRIVCFGR1_PRIV18 STM32_EXTI_BIT(18) +#define EXTI_PRIVCFGR1_PRIV19 STM32_EXTI_BIT(19) +#define EXTI_PRIVCFGR1_PRIV20 STM32_EXTI_BIT(20) +#define EXTI_PRIVCFGR1_PRIV21 STM32_EXTI_BIT(21) +#define EXTI_PRIVCFGR1_PRIV22 STM32_EXTI_BIT(22) +#define EXTI_PRIVCFGR1_PRIV23 STM32_EXTI_BIT(23) +#define EXTI_PRIVCFGR1_PRIV24 STM32_EXTI_BIT(24) +#define EXTI_PRIVCFGR1_PRIV25 STM32_EXTI_BIT(25) +#define EXTI_PRIVCFGR1_PRIV26 STM32_EXTI_BIT(26) +#define EXTI_PRIVCFGR1_PRIV27 STM32_EXTI_BIT(27) +#define EXTI_PRIVCFGR1_PRIV28 STM32_EXTI_BIT(28) +#define EXTI_PRIVCFGR1_PRIV29 STM32_EXTI_BIT(29) +#define EXTI_PRIVCFGR1_PRIV30 STM32_EXTI_BIT(30) +#define EXTI_PRIVCFGR1_PRIV31 STM32_EXTI_BIT(31) + +/* EXTI privilege configuration register 2 */ + +#define EXTI_PRIVCFGR2_PRIV32 STM32_EXTI_BIT(32) +#define EXTI_PRIVCFGR2_PRIV33 STM32_EXTI_BIT(33) +#define EXTI_PRIVCFGR2_PRIV34 STM32_EXTI_BIT(34) +#define EXTI_PRIVCFGR2_PRIV35 STM32_EXTI_BIT(35) +#define EXTI_PRIVCFGR2_PRIV36 STM32_EXTI_BIT(36) +#define EXTI_PRIVCFGR2_PRIV37 STM32_EXTI_BIT(37) +#define EXTI_PRIVCFGR2_PRIV38 STM32_EXTI_BIT(38) +#define EXTI_PRIVCFGR2_PRIV39 STM32_EXTI_BIT(39) +#define EXTI_PRIVCFGR2_PRIV40 STM32_EXTI_BIT(40) +#define EXTI_PRIVCFGR2_PRIV41 STM32_EXTI_BIT(41) +#define EXTI_PRIVCFGR2_PRIV42 STM32_EXTI_BIT(42) +#define EXTI_PRIVCFGR2_PRIV43 STM32_EXTI_BIT(43) +#define EXTI_PRIVCFGR2_PRIV44 STM32_EXTI_BIT(44) +#define EXTI_PRIVCFGR2_PRIV45 STM32_EXTI_BIT(45) +#define EXTI_PRIVCFGR2_PRIV46 STM32_EXTI_BIT(46) +#define EXTI_PRIVCFGR2_PRIV47 STM32_EXTI_BIT(47) +#define EXTI_PRIVCFGR2_PRIV48 STM32_EXTI_BIT(48) +#define EXTI_PRIVCFGR2_PRIV49 STM32_EXTI_BIT(49) +#define EXTI_PRIVCFGR2_PRIV50 STM32_EXTI_BIT(50) +#define EXTI_PRIVCFGR2_PRIV51 STM32_EXTI_BIT(51) +#define EXTI_PRIVCFGR2_PRIV52 STM32_EXTI_BIT(52) +#define EXTI_PRIVCFGR2_PRIV53 STM32_EXTI_BIT(53) +#define EXTI_PRIVCFGR2_PRIV54 STM32_EXTI_BIT(54) +#define EXTI_PRIVCFGR2_PRIV55 STM32_EXTI_BIT(55) +#define EXTI_PRIVCFGR2_PRIV56 STM32_EXTI_BIT(56) +#define EXTI_PRIVCFGR2_PRIV57 STM32_EXTI_BIT(57) +#define EXTI_PRIVCFGR2_PRIV58 STM32_EXTI_BIT(58) +#define EXTI_PRIVCFGR2_PRIV59 STM32_EXTI_BIT(59) +#define EXTI_PRIVCFGR2_PRIV60 STM32_EXTI_BIT(60) +#define EXTI_PRIVCFGR2_PRIV61 STM32_EXTI_BIT(61) +#define EXTI_PRIVCFGR2_PRIV62 STM32_EXTI_BIT(62) +#define EXTI_PRIVCFGR2_PRIV63 STM32_EXTI_BIT(63) + +/* EXTI CPU wake-up with interrupt mask register 1 */ + +#define EXTI_IMR1_IM0 STM32_EXTI_BIT(0) +#define EXTI_IMR1_IM1 STM32_EXTI_BIT(1) +#define EXTI_IMR1_IM2 STM32_EXTI_BIT(2) +#define EXTI_IMR1_IM3 STM32_EXTI_BIT(3) +#define EXTI_IMR1_IM4 STM32_EXTI_BIT(4) +#define EXTI_IMR1_IM5 STM32_EXTI_BIT(5) +#define EXTI_IMR1_IM6 STM32_EXTI_BIT(6) +#define EXTI_IMR1_IM7 STM32_EXTI_BIT(7) +#define EXTI_IMR1_IM8 STM32_EXTI_BIT(8) +#define EXTI_IMR1_IM9 STM32_EXTI_BIT(9) +#define EXTI_IMR1_IM10 STM32_EXTI_BIT(10) +#define EXTI_IMR1_IM11 STM32_EXTI_BIT(11) +#define EXTI_IMR1_IM12 STM32_EXTI_BIT(12) +#define EXTI_IMR1_IM13 STM32_EXTI_BIT(13) +#define EXTI_IMR1_IM14 STM32_EXTI_BIT(14) +#define EXTI_IMR1_IM15 STM32_EXTI_BIT(15) +#define EXTI_IMR1_IM16 STM32_EXTI_BIT(16) +#define EXTI_IMR1_IM17 STM32_EXTI_BIT(17) +#define EXTI_IMR1_IM18 STM32_EXTI_BIT(18) +#define EXTI_IMR1_IM19 STM32_EXTI_BIT(19) +#define EXTI_IMR1_IM20 STM32_EXTI_BIT(20) +#define EXTI_IMR1_IM21 STM32_EXTI_BIT(21) +#define EXTI_IMR1_IM22 STM32_EXTI_BIT(22) +#define EXTI_IMR1_IM23 STM32_EXTI_BIT(23) +#define EXTI_IMR1_IM24 STM32_EXTI_BIT(24) +#define EXTI_IMR1_IM25 STM32_EXTI_BIT(25) +#define EXTI_IMR1_IM26 STM32_EXTI_BIT(26) +#define EXTI_IMR1_IM27 STM32_EXTI_BIT(27) +#define EXTI_IMR1_IM28 STM32_EXTI_BIT(28) +#define EXTI_IMR1_IM29 STM32_EXTI_BIT(29) +#define EXTI_IMR1_IM30 STM32_EXTI_BIT(30) +#define EXTI_IMR1_IM31 STM32_EXTI_BIT(31) + +/* EXTI CPU wake-up with interrupt mask register 2 */ + +#define EXTI_IMR2_IM32 STM32_EXTI_BIT(32) +#define EXTI_IMR2_IM33 STM32_EXTI_BIT(33) +#define EXTI_IMR2_IM34 STM32_EXTI_BIT(34) +#define EXTI_IMR2_IM35 STM32_EXTI_BIT(35) +#define EXTI_IMR2_IM36 STM32_EXTI_BIT(36) +#define EXTI_IMR2_IM37 STM32_EXTI_BIT(37) +#define EXTI_IMR2_IM38 STM32_EXTI_BIT(38) +#define EXTI_IMR2_IM39 STM32_EXTI_BIT(39) +#define EXTI_IMR2_IM40 STM32_EXTI_BIT(40) +#define EXTI_IMR2_IM41 STM32_EXTI_BIT(41) +#define EXTI_IMR2_IM42 STM32_EXTI_BIT(42) +#define EXTI_IMR2_IM43 STM32_EXTI_BIT(43) +#define EXTI_IMR2_IM44 STM32_EXTI_BIT(44) +#define EXTI_IMR2_IM45 STM32_EXTI_BIT(45) +#define EXTI_IMR2_IM46 STM32_EXTI_BIT(46) +#define EXTI_IMR2_IM47 STM32_EXTI_BIT(47) +#define EXTI_IMR2_IM48 STM32_EXTI_BIT(48) +#define EXTI_IMR2_IM49 STM32_EXTI_BIT(49) +#define EXTI_IMR2_IM50 STM32_EXTI_BIT(50) +#define EXTI_IMR2_IM51 STM32_EXTI_BIT(51) +#define EXTI_IMR2_IM52 STM32_EXTI_BIT(52) +#define EXTI_IMR2_IM53 STM32_EXTI_BIT(53) +#define EXTI_IMR2_IM54 STM32_EXTI_BIT(54) +#define EXTI_IMR2_IM55 STM32_EXTI_BIT(55) +#define EXTI_IMR2_IM56 STM32_EXTI_BIT(56) +#define EXTI_IMR2_IM57 STM32_EXTI_BIT(57) +#define EXTI_IMR2_IM58 STM32_EXTI_BIT(58) +#define EXTI_IMR2_IM59 STM32_EXTI_BIT(59) +#define EXTI_IMR2_IM60 STM32_EXTI_BIT(60) +#define EXTI_IMR2_IM61 STM32_EXTI_BIT(61) +#define EXTI_IMR2_IM62 STM32_EXTI_BIT(62) +#define EXTI_IMR2_IM63 STM32_EXTI_BIT(63) + +/* EXTI CPU wake-up with event mask register 1 */ + +#define EXTI_EMR1_EM0 STM32_EXTI_BIT(0) +#define EXTI_EMR1_EM1 STM32_EXTI_BIT(1) +#define EXTI_EMR1_EM2 STM32_EXTI_BIT(2) +#define EXTI_EMR1_EM3 STM32_EXTI_BIT(3) +#define EXTI_EMR1_EM4 STM32_EXTI_BIT(4) +#define EXTI_EMR1_EM5 STM32_EXTI_BIT(5) +#define EXTI_EMR1_EM6 STM32_EXTI_BIT(6) +#define EXTI_EMR1_EM7 STM32_EXTI_BIT(7) +#define EXTI_EMR1_EM8 STM32_EXTI_BIT(8) +#define EXTI_EMR1_EM9 STM32_EXTI_BIT(9) +#define EXTI_EMR1_EM10 STM32_EXTI_BIT(10) +#define EXTI_EMR1_EM11 STM32_EXTI_BIT(11) +#define EXTI_EMR1_EM12 STM32_EXTI_BIT(12) +#define EXTI_EMR1_EM13 STM32_EXTI_BIT(13) +#define EXTI_EMR1_EM14 STM32_EXTI_BIT(14) +#define EXTI_EMR1_EM15 STM32_EXTI_BIT(15) +#define EXTI_EMR1_EM16 STM32_EXTI_BIT(16) +#define EXTI_EMR1_EM17 STM32_EXTI_BIT(17) +#define EXTI_EMR1_EM18 STM32_EXTI_BIT(18) +#define EXTI_EMR1_EM19 STM32_EXTI_BIT(19) +#define EXTI_EMR1_EM20 STM32_EXTI_BIT(20) +#define EXTI_EMR1_EM21 STM32_EXTI_BIT(21) +#define EXTI_EMR1_EM22 STM32_EXTI_BIT(22) +#define EXTI_EMR1_EM23 STM32_EXTI_BIT(23) +#define EXTI_EMR1_EM24 STM32_EXTI_BIT(24) +#define EXTI_EMR1_EM25 STM32_EXTI_BIT(25) +#define EXTI_EMR1_EM26 STM32_EXTI_BIT(26) +#define EXTI_EMR1_EM27 STM32_EXTI_BIT(27) +#define EXTI_EMR1_EM28 STM32_EXTI_BIT(28) +#define EXTI_EMR1_EM29 STM32_EXTI_BIT(29) +#define EXTI_EMR1_EM30 STM32_EXTI_BIT(30) +#define EXTI_EMR1_EM31 STM32_EXTI_BIT(31) + +/* EXTI CPU wake-up with event mask register 2 */ + +#define EXTI_EMR2_EM32 STM32_EXTI_BIT(32) +#define EXTI_EMR2_EM33 STM32_EXTI_BIT(33) +#define EXTI_EMR2_EM34 STM32_EXTI_BIT(34) +#define EXTI_EMR2_EM35 STM32_EXTI_BIT(35) +#define EXTI_EMR2_EM36 STM32_EXTI_BIT(36) +#define EXTI_EMR2_EM37 STM32_EXTI_BIT(37) +#define EXTI_EMR2_EM38 STM32_EXTI_BIT(38) +#define EXTI_EMR2_EM39 STM32_EXTI_BIT(39) +#define EXTI_EMR2_EM40 STM32_EXTI_BIT(40) +#define EXTI_EMR2_EM41 STM32_EXTI_BIT(41) +#define EXTI_EMR2_EM42 STM32_EXTI_BIT(42) +#define EXTI_EMR2_EM43 STM32_EXTI_BIT(43) +#define EXTI_EMR2_EM44 STM32_EXTI_BIT(44) +#define EXTI_EMR2_EM45 STM32_EXTI_BIT(45) +#define EXTI_EMR2_EM46 STM32_EXTI_BIT(46) +#define EXTI_EMR2_EM47 STM32_EXTI_BIT(47) +#define EXTI_EMR2_EM48 STM32_EXTI_BIT(48) +#define EXTI_EMR2_EM49 STM32_EXTI_BIT(49) +#define EXTI_EMR2_EM50 STM32_EXTI_BIT(50) +#define EXTI_EMR2_EM51 STM32_EXTI_BIT(51) +#define EXTI_EMR2_EM52 STM32_EXTI_BIT(52) +#define EXTI_EMR2_EM53 STM32_EXTI_BIT(53) +#define EXTI_EMR2_EM54 STM32_EXTI_BIT(54) +#define EXTI_EMR2_EM55 STM32_EXTI_BIT(55) +#define EXTI_EMR2_EM56 STM32_EXTI_BIT(56) +#define EXTI_EMR2_EM57 STM32_EXTI_BIT(57) +#define EXTI_EMR2_EM58 STM32_EXTI_BIT(58) +#define EXTI_EMR2_EM59 STM32_EXTI_BIT(59) +#define EXTI_EMR2_EM60 STM32_EXTI_BIT(60) +#define EXTI_EMR2_EM61 STM32_EXTI_BIT(61) +#define EXTI_EMR2_EM62 STM32_EXTI_BIT(62) +#define EXTI_EMR2_EM63 STM32_EXTI_BIT(63) + +/* GPIO lines 0-15 have four port selections per EXTICR, eight bits apart. + * Clear the whole selector byte. Valid port encodings leave any unused + * upper bits at their reset value of zero. + */ + +#define STM32_EXTI_EXTICR(n) (STM32_EXTI_EXTICR1 + (((n) >> 2) << 2)) +#define EXTI_EXTICR_SHIFT(n) (((n) & 3) << 3) +#define EXTI_EXTICR_MASK(n) (0xffu << EXTI_EXTICR_SHIFT(n)) +#define EXTI_EXTICR_PORT(n, p) ((p) << EXTI_EXTICR_SHIFT(n)) + +/* EXTI external interrupt selection register 1 */ + +#define EXTI_EXTICR1_EXTI0_SHIFT EXTI_EXTICR_SHIFT(0) +#define EXTI_EXTICR1_EXTI0_MASK EXTI_EXTICR_MASK(0) +#define EXTI_EXTICR1_EXTI0(n) EXTI_EXTICR_PORT(0, n) +#define EXTI_EXTICR1_EXTI1_SHIFT EXTI_EXTICR_SHIFT(1) +#define EXTI_EXTICR1_EXTI1_MASK EXTI_EXTICR_MASK(1) +#define EXTI_EXTICR1_EXTI1(n) EXTI_EXTICR_PORT(1, n) +#define EXTI_EXTICR1_EXTI2_SHIFT EXTI_EXTICR_SHIFT(2) +#define EXTI_EXTICR1_EXTI2_MASK EXTI_EXTICR_MASK(2) +#define EXTI_EXTICR1_EXTI2(n) EXTI_EXTICR_PORT(2, n) +#define EXTI_EXTICR1_EXTI3_SHIFT EXTI_EXTICR_SHIFT(3) +#define EXTI_EXTICR1_EXTI3_MASK EXTI_EXTICR_MASK(3) +#define EXTI_EXTICR1_EXTI3(n) EXTI_EXTICR_PORT(3, n) + +/* EXTI external interrupt selection register 2 */ + +#define EXTI_EXTICR2_EXTI4_SHIFT EXTI_EXTICR_SHIFT(4) +#define EXTI_EXTICR2_EXTI4_MASK EXTI_EXTICR_MASK(4) +#define EXTI_EXTICR2_EXTI4(n) EXTI_EXTICR_PORT(4, n) +#define EXTI_EXTICR2_EXTI5_SHIFT EXTI_EXTICR_SHIFT(5) +#define EXTI_EXTICR2_EXTI5_MASK EXTI_EXTICR_MASK(5) +#define EXTI_EXTICR2_EXTI5(n) EXTI_EXTICR_PORT(5, n) +#define EXTI_EXTICR2_EXTI6_SHIFT EXTI_EXTICR_SHIFT(6) +#define EXTI_EXTICR2_EXTI6_MASK EXTI_EXTICR_MASK(6) +#define EXTI_EXTICR2_EXTI6(n) EXTI_EXTICR_PORT(6, n) +#define EXTI_EXTICR2_EXTI7_SHIFT EXTI_EXTICR_SHIFT(7) +#define EXTI_EXTICR2_EXTI7_MASK EXTI_EXTICR_MASK(7) +#define EXTI_EXTICR2_EXTI7(n) EXTI_EXTICR_PORT(7, n) + +/* EXTI external interrupt selection register 3 */ + +#define EXTI_EXTICR3_EXTI8_SHIFT EXTI_EXTICR_SHIFT(8) +#define EXTI_EXTICR3_EXTI8_MASK EXTI_EXTICR_MASK(8) +#define EXTI_EXTICR3_EXTI8(n) EXTI_EXTICR_PORT(8, n) +#define EXTI_EXTICR3_EXTI9_SHIFT EXTI_EXTICR_SHIFT(9) +#define EXTI_EXTICR3_EXTI9_MASK EXTI_EXTICR_MASK(9) +#define EXTI_EXTICR3_EXTI9(n) EXTI_EXTICR_PORT(9, n) +#define EXTI_EXTICR3_EXTI10_SHIFT EXTI_EXTICR_SHIFT(10) +#define EXTI_EXTICR3_EXTI10_MASK EXTI_EXTICR_MASK(10) +#define EXTI_EXTICR3_EXTI10(n) EXTI_EXTICR_PORT(10, n) +#define EXTI_EXTICR3_EXTI11_SHIFT EXTI_EXTICR_SHIFT(11) +#define EXTI_EXTICR3_EXTI11_MASK EXTI_EXTICR_MASK(11) +#define EXTI_EXTICR3_EXTI11(n) EXTI_EXTICR_PORT(11, n) + +/* EXTI external interrupt selection register 4 */ + +#define EXTI_EXTICR4_EXTI12_SHIFT EXTI_EXTICR_SHIFT(12) +#define EXTI_EXTICR4_EXTI12_MASK EXTI_EXTICR_MASK(12) +#define EXTI_EXTICR4_EXTI12(n) EXTI_EXTICR_PORT(12, n) +#define EXTI_EXTICR4_EXTI13_SHIFT EXTI_EXTICR_SHIFT(13) +#define EXTI_EXTICR4_EXTI13_MASK EXTI_EXTICR_MASK(13) +#define EXTI_EXTICR4_EXTI13(n) EXTI_EXTICR_PORT(13, n) +#define EXTI_EXTICR4_EXTI14_SHIFT EXTI_EXTICR_SHIFT(14) +#define EXTI_EXTICR4_EXTI14_MASK EXTI_EXTICR_MASK(14) +#define EXTI_EXTICR4_EXTI14(n) EXTI_EXTICR_PORT(14, n) +#define EXTI_EXTICR4_EXTI15_SHIFT EXTI_EXTICR_SHIFT(15) +#define EXTI_EXTICR4_EXTI15_MASK EXTI_EXTICR_MASK(15) +#define EXTI_EXTICR4_EXTI15(n) EXTI_EXTICR_PORT(15, n) /* EXTI lock register */ #define EXTI_LOCKR_LOCK (1 << 0) -/* EXTI CPU wake-up with interrupt mask register */ - -#define EXTI_IMR1_IM0 (1 << 0) -#define EXTI_IMR1_IM1 (1 << 1) -#define EXTI_IMR1_IM2 (1 << 2) -#define EXTI_IMR1_IM3 (1 << 3) -#define EXTI_IMR1_IM4 (1 << 4) -#define EXTI_IMR1_IM5 (1 << 5) -#define EXTI_IMR1_IM6 (1 << 6) -#define EXTI_IMR1_IM7 (1 << 7) -#define EXTI_IMR1_IM8 (1 << 8) -#define EXTI_IMR1_IM9 (1 << 9) -#define EXTI_IMR1_IM10 (1 << 10) -#define EXTI_IMR1_IM11 (1 << 11) -#define EXTI_IMR1_IM12 (1 << 12) -#define EXTI_IMR1_IM13 (1 << 13) -#define EXTI_IMR1_IM14 (1 << 14) -#define EXTI_IMR1_IM15 (1 << 15) -#define EXTI_IMR1_IM16 (1 << 16) -#define EXTI_IMR1_IM17 (1 << 17) -#define EXTI_IMR1_IM18 (1 << 18) -#define EXTI_IMR1_IM19 (1 << 19) -#define EXTI_IMR1_IM20 (1 << 20) -#define EXTI_IMR1_IM21 (1 << 21) -#define EXTI_IMR1_IM22 (1 << 22) -#if STM32_EXTI_NLINES > 23 -#define EXTI_IMR1_IM23 (1 << 23) -#endif -#if STM32_EXTI_NLINES > 24 -#define EXTI_IMR1_IM24 (1 << 24) -#endif -#if STM32_EXTI_NLINES > 25 -#define EXTI_IMR1_IM25 (1 << 25) -#endif - -/* EXTI CPU wake-up with event mask register */ - -#define EXTI_EMR1_EM0 (1 << 0) -#define EXTI_EMR1_EM1 (1 << 1) -#define EXTI_EMR1_EM2 (1 << 2) -#define EXTI_EMR1_EM3 (1 << 3) -#define EXTI_EMR1_EM4 (1 << 4) -#define EXTI_EMR1_EM5 (1 << 5) -#define EXTI_EMR1_EM6 (1 << 6) -#define EXTI_EMR1_EM7 (1 << 7) -#define EXTI_EMR1_EM8 (1 << 8) -#define EXTI_EMR1_EM9 (1 << 9) -#define EXTI_EMR1_EM10 (1 << 10) -#define EXTI_EMR1_EM11 (1 << 11) -#define EXTI_EMR1_EM12 (1 << 12) -#define EXTI_EMR1_EM13 (1 << 13) -#define EXTI_EMR1_EM14 (1 << 14) -#define EXTI_EMR1_EM15 (1 << 15) -#define EXTI_EMR1_EM16 (1 << 16) -#define EXTI_EMR1_EM17 (1 << 17) -#define EXTI_EMR1_EM18 (1 << 18) -#define EXTI_EMR1_EM19 (1 << 19) -#define EXTI_EMR1_EM20 (1 << 20) -#define EXTI_EMR1_EM21 (1 << 21) -#define EXTI_EMR1_EM22 (1 << 22) -#if STM32_EXTI_NLINES > 23 -#define EXTI_EMR1_EM23 (1 << 23) -#endif -#if STM32_EXTI_NLINES > 24 -#define EXTI_EMR1_EM24 (1 << 24) -#endif -#if STM32_EXTI_NLINES > 25 -#define EXTI_EMR1_EM25 (1 << 25) -#endif - -/* GPIO port selection occupies four bits in each EXTICR field. */ - -#define STM32_EXTI_EXTICR_PORT_MASK 0xff - #endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_M33_V1_H */ diff --git a/arch/arm/src/common/stm32/stm32_exti_gpio_m33_v1.c b/arch/arm/src/common/stm32/stm32_exti_gpio_m33_v1.c index 060159ea8d3..b2d81d5622a 100644 --- a/arch/arm/src/common/stm32/stm32_exti_gpio_m33_v1.c +++ b/arch/arm/src/common/stm32/stm32_exti_gpio_m33_v1.c @@ -77,8 +77,8 @@ static int stm32_exti0_15_isr(int irq, void *context, void *arg) /* Clear the pending interrupt for both rising and falling edges. */ - putreg32(0x0001 << exti, STM32_EXTI_RPR1); - putreg32(0x0001 << exti, STM32_EXTI_FPR1); + putreg32(STM32_EXTI_BIT(exti), STM32_EXTI_RPR1); + putreg32(STM32_EXTI_BIT(exti), STM32_EXTI_FPR1); /* And dispatch the interrupt to the handler */ @@ -123,10 +123,8 @@ static int stm32_exti0_15_isr(int irq, void *context, void *arg) int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { - uint32_t exticr; uint32_t exti; uint32_t port; - uint32_t shift; uint32_t pin; int irq; int ret; @@ -139,7 +137,7 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, return -EINVAL; } - exti = 1u << pin; + exti = STM32_EXTI_BIT(pin); irq = STM32_IRQ_EXTI0 + pin; g_gpio_handlers[pin].callback = func; @@ -147,10 +145,8 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Route the EXTI line to the selected GPIO port. */ - exticr = STM32_EXTI_EXTICR1 + ((pin >> 2) << 2); - shift = (pin & 3) << 3; - modifyreg32(exticr, STM32_EXTI_EXTICR_PORT_MASK << shift, - (event || func) ? port << shift : 0); + modifyreg32(STM32_EXTI_EXTICR(pin), EXTI_EXTICR_MASK(pin), + (event || func) ? EXTI_EXTICR_PORT(pin, port) : 0); /* Install external interrupt handlers */ diff --git a/arch/arm/src/stm32l5/CMakeLists.txt b/arch/arm/src/stm32l5/CMakeLists.txt index cfd801d08ab..af7b024b019 100644 --- a/arch/arm/src/stm32l5/CMakeLists.txt +++ b/arch/arm/src/stm32l5/CMakeLists.txt @@ -26,8 +26,6 @@ list( APPEND SRCS stm32l5_allocateheap.c - stm32l5_exti_gpio.c - stm32l5_gpio.c stm32l5_irq.c stm32l5_lowputc.c stm32l5_rcc.c diff --git a/arch/arm/src/stm32l5/Kconfig b/arch/arm/src/stm32l5/Kconfig index a41fb1c522d..e12c16cbf11 100644 --- a/arch/arm/src/stm32l5/Kconfig +++ b/arch/arm/src/stm32l5/Kconfig @@ -10,6 +10,8 @@ comment "STM32L5 Configuration Options" config STM32_L5_PERIPHERALS bool default y + select STM32_HAVE_IP_EXTI_M33_V1 + select STM32_HAVE_IP_GPIO_M33_V1 select STM32_HAVE_RTC_SUBSECONDS select STM32_HAVE_RTC_MAGIC select STM32_HAVE_RTC diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs index b01e736c4c8..7b2cb2f6cf7 100644 --- a/arch/arm/src/stm32l5/Make.defs +++ b/arch/arm/src/stm32l5/Make.defs @@ -33,7 +33,7 @@ include common/stm32/Make.defs # Required STM32L5 files CHIP_ASRCS = -CHIP_CSRCS += stm32l5_allocateheap.c stm32l5_exti_gpio.c stm32l5_gpio.c +CHIP_CSRCS += stm32l5_allocateheap.c CHIP_CSRCS += stm32l5_irq.c stm32l5_lowputc.c stm32l5_rcc.c CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c stm32l5_lsi.c diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_exti.h b/arch/arm/src/stm32l5/hardware/stm32l5_exti.h deleted file mode 100644 index 11b113e55e5..00000000000 --- a/arch/arm/src/stm32l5/hardware/stm32l5_exti.h +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/hardware/stm32l5_exti.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */ -#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */ -#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */ -#define STM32_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */ -#define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */ -#define STM32_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */ -#define STM32_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */ -#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */ -#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */ -#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */ -#define STM32_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */ -#define STM32_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */ -#define STM32_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */ -#define STM32_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */ -#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */ -#define STM32_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */ -#define STM32_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */ -#define STM32_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */ -#define STM32_EXTI_LOCKR_OFFSET 0x0070 /* Lock */ -#define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */ -#define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */ -#define STM32_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */ -#define STM32_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */ - -/* Register Addresses *******************************************************/ - -#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET) -#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET) -#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET) -#define STM32_EXTI_RPR1 (STM32_EXTI_BASE + STM32_EXTI_RPR1_OFFSET) -#define STM32_EXTI_FPR1 (STM32_EXTI_BASE + STM32_EXTI_FPR1_OFFSET) -#define STM32_EXTI_SECCFGR1 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR1_OFFSET) -#define STM32_EXTI_PRIVCFGR1 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR1_OFFSET) -#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET) -#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET) -#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET) -#define STM32_EXTI_RPR2 (STM32_EXTI_BASE + STM32_EXTI_RPR2_OFFSET) -#define STM32_EXTI_FPR2 (STM32_EXTI_BASE + STM32_EXTI_FPR2_OFFSET) -#define STM32_EXTI_SECCFGR2 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR2_OFFSET) -#define STM32_EXTI_PRIVCFGR2 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR2_OFFSET) -#define STM32_EXTI_EXTICR1 (STM32_EXTI_BASE + STM32_EXTI_EXTICR1_OFFSET) -#define STM32_EXTI_EXTICR2 (STM32_EXTI_BASE + STM32_EXTI_EXTICR2_OFFSET) -#define STM32_EXTI_EXTICR3 (STM32_EXTI_BASE + STM32_EXTI_EXTICR3_OFFSET) -#define STM32_EXTI_EXTICR4 (STM32_EXTI_BASE + STM32_EXTI_EXTICR4_OFFSET) -#define STM32_EXTI_LOCKR (STM32_EXTI_BASE + STM32_EXTI_LOCKR_OFFSET) -#define STM32_EXTI_IMR1 (STM32_EXTI_BASE + STM32_EXTI_IMR1_OFFSET) -#define STM32_EXTI_EMR1 (STM32_EXTI_BASE + STM32_EXTI_EMR1_OFFSET) -#define STM32_EXTI_IMR2 (STM32_EXTI_BASE + STM32_EXTI_IMR2_OFFSET) -#define STM32_EXTI_EMR2 (STM32_EXTI_BASE + STM32_EXTI_EMR2_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* EXTI lines > 15 are associated with internal devices: */ - -#define EXTI1_PVD (1 << 16) /* EXTI line 16: PVD output */ -#define EXTI1_RTC (1 << 17) /* EXTI line 17: RTC */ -#define EXTI1_RTC_SECURE (1 << 18) /* EXTI line 18: RTC secure */ -#define EXTI1_TAMP (1 << 19) /* EXTI line 19: TAMP */ -#define EXTI1_TAMP_SECURE (1 << 20) /* EXTI line 20: TAMP secure */ -#define EXTI1_COMP1 (1 << 21) /* EXTI line 21: COMP1 output */ -#define EXTI1_COMP2 (1 << 22) /* EXTI line 22: COMP2 output */ -#define EXTI1_I2C1 (1 << 23) /* EXTI line 23: I2C1 wakeup */ -#define EXTI1_I2C2 (1 << 24) /* EXTI line 24: I2C2 wakeup */ -#define EXTI1_I2C3 (1 << 25) /* EXTI line 25: I2C3 wakeup */ -#define EXTI1_USART1 (1 << 26) /* EXTI line 26: USART1 wakeup */ -#define EXTI1_USART2 (1 << 27) /* EXTI line 27: USART2 wakeup */ -#define EXTI1_USART3 (1 << 28) /* EXTI line 28: USART3 wakeup */ -#define EXTI1_USART4 (1 << 29) /* EXTI line 29: USART4 wakeup */ -#define EXTI1_USART5 (1 << 30) /* EXTI line 30: USART5 wakeup */ -#define EXTI1_LPUART1 (1 << 31) /* EXTI line 31: LPUART1 wakeup */ -#define EXTI2_LPTIM1 (1 << 0) /* EXTI line 32: LPTIM1 */ -#define EXTI2_LPTIM2 (1 << 1) /* EXTI line 33: LPTIM2 */ -#define EXTI2_USBFS (1 << 2) /* EXTI line 34: USB FS wakeup */ -#define EXTI2_PVM1 (1 << 3) /* EXTI line 35: PVM1 wakeup */ -#define EXTI2_PVM2 (1 << 4) /* EXTI line 36: PVM2 wakeup */ -#define EXTI2_PVM3 (1 << 5) /* EXTI line 37: PVM3 wakeup */ -#define EXTI2_PVM4 (1 << 6) /* EXTI line 38: PVM4 wakeup */ -#define EXTI2_RSVD (1 << 7) /* EXTI line 39: reserved */ -#define EXTI2_I2C4 (1 << 8) /* EXTI line 40: I2C4 wakeup */ -#define EXTI2_UCPD1 (1 << 9) /* EXTI line 41: UCPD1 wakeup */ -#define EXTI2_LPTIM3 (1 << 10) /* EXTI line 42: LPTIM3 wakeup */ - -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h b/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h deleted file mode 100644 index 7b4d880bca0..00000000000 --- a/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h +++ /dev/null @@ -1,389 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/hardware/stm32l5_gpio.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> -#include <arch/stm32l5/chip.h> - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ -#define STM32_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NPORTS > 0 -# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 1 -# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 2 -# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 3 -# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 4 -# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 5 -# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOF_BRR (STM32_GPIOF_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 6 -# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOG_IDR (STM32_GPIOG_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOG_ODR (STM32_GPIOG_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOG_BRR (STM32_GPIOG_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 7 -# define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 8 -# define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOI_IDR (STM32_GPIOI_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOI_ODR (STM32_GPIOI_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOI_BRR (STM32_GPIOI_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOI_SECCFGR (STM32_GPIOI_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* GPIO port mode register */ - -#define GPIO_MODER_INPUT (0) /* Input */ -#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */ -#define GPIO_MODER_ALT (2) /* Alternate mode */ -#define GPIO_MODER_ANALOG (3) /* Analog mode */ - -#define GPIO_MODER_SHIFT(n) ((n) << 1) -#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n)) - -#define GPIO_MODER0_SHIFT (0) -#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT) -#define GPIO_MODER1_SHIFT (2) -#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT) -#define GPIO_MODER2_SHIFT (4) -#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT) -#define GPIO_MODER3_SHIFT (6) -#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT) -#define GPIO_MODER4_SHIFT (8) -#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT) -#define GPIO_MODER5_SHIFT (10) -#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT) -#define GPIO_MODER6_SHIFT (12) -#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT) -#define GPIO_MODER7_SHIFT (14) -#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT) -#define GPIO_MODER8_SHIFT (16) -#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT) -#define GPIO_MODER9_SHIFT (18) -#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT) -#define GPIO_MODER10_SHIFT (20) -#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT) -#define GPIO_MODER11_SHIFT (22) -#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT) -#define GPIO_MODER12_SHIFT (24) -#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT) -#define GPIO_MODER13_SHIFT (26) -#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT) -#define GPIO_MODER14_SHIFT (28) -#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT) -#define GPIO_MODER15_SHIFT (30) -#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT) - -/* GPIO port output type register */ - -#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */ -#define GPIO_OTYPER_PP(n) (0) /* 0=Output push-pull */ - -/* GPIO port output speed register */ - -#define GPIO_OSPEED_2MHZ (0) /* 2 MHz Low speed */ -#define GPIO_OSPEED_25MHZ (1) /* 25 MHz Medium speed */ -#define GPIO_OSPEED_50MHZ (2) /* 50 MHz High speed */ -#define GPIO_OSPEED_100MHZ (3) /* 100 MHz Very High speed on 30 pF (80 MHz Output max speed on 15 pF) */ - -#define GPIO_OSPEED_SHIFT(n) ((n) << 1) -#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n)) - -#define GPIO_OSPEED0_SHIFT (0) -#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT) -#define GPIO_OSPEED1_SHIFT (2) -#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT) -#define GPIO_OSPEED2_SHIFT (4) -#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT) -#define GPIO_OSPEED3_SHIFT (6) -#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT) -#define GPIO_OSPEED4_SHIFT (8) -#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT) -#define GPIO_OSPEED5_SHIFT (10) -#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT) -#define GPIO_OSPEED6_SHIFT (12) -#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT) -#define GPIO_OSPEED7_SHIFT (14) -#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT) -#define GPIO_OSPEED8_SHIFT (16) -#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT) -#define GPIO_OSPEED9_SHIFT (18) -#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT) -#define GPIO_OSPEED10_SHIFT (20) -#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT) -#define GPIO_OSPEED11_SHIFT (22) -#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT) -#define GPIO_OSPEED12_SHIFT (24) -#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT) -#define GPIO_OSPEED13_SHIFT (26) -#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT) -#define GPIO_OSPEED14_SHIFT (28) -#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT) -#define GPIO_OSPEED15_SHIFT (30) -#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT) - -/* GPIO port pull-up/pull-down register */ - -#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */ -#define GPIO_PUPDR_PULLUP (1) /* Pull-up */ -#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */ - -#define GPIO_PUPDR_SHIFT(n) ((n) << 1) -#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n)) - -#define GPIO_PUPDR0_SHIFT (0) -#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT) -#define GPIO_PUPDR1_SHIFT (2) -#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT) -#define GPIO_PUPDR2_SHIFT (4) -#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT) -#define GPIO_PUPDR3_SHIFT (6) -#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT) -#define GPIO_PUPDR4_SHIFT (8) -#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT) -#define GPIO_PUPDR5_SHIFT (10) -#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT) -#define GPIO_PUPDR6_SHIFT (12) -#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT) -#define GPIO_PUPDR7_SHIFT (14) -#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT) -#define GPIO_PUPDR8_SHIFT (16) -#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT) -#define GPIO_PUPDR9_SHIFT (18) -#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT) -#define GPIO_PUPDR10_SHIFT (20) -#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT) -#define GPIO_PUPDR11_SHIFT (22) -#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT) -#define GPIO_PUPDR12_SHIFT (24) -#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT) -#define GPIO_PUPDR13_SHIFT (26) -#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT) -#define GPIO_PUPDR14_SHIFT (28) -#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT) -#define GPIO_PUPDR15_SHIFT (30) -#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT) - -/* GPIO port input data register */ - -#define GPIO_IDR(n) (1 << (n)) - -/* GPIO port output data register */ - -#define GPIO_ODR(n) (1 << (n)) - -/* GPIO port bit set/reset register */ - -#define GPIO_BSRR_SET(n) (1 << (n)) -#define GPIO_BSRR_RESET(n) (1 << ((n)+16)) - -/* GPIO port configuration lock register */ - -#define GPIO_LCKR(n) (1 << (n)) -#define GPIO_LCKK (1 << 16) /* Lock key */ - -/* GPIO alternate function low/high register */ - -#define GPIO_AFR_SHIFT(n) ((n) << 2) -#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n)) - -#define GPIO_AFRL0_SHIFT (0) -#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT) -#define GPIO_AFRL1_SHIFT (4) -#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT) -#define GPIO_AFRL2_SHIFT (8) -#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT) -#define GPIO_AFRL3_SHIFT (12) -#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT) -#define GPIO_AFRL4_SHIFT (16) -#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT) -#define GPIO_AFRL5_SHIFT (20) -#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT) -#define GPIO_AFRL6_SHIFT (24) -#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT) -#define GPIO_AFRL7_SHIFT (28) -#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT) - -#define GPIO_AFRH8_SHIFT (0) -#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT) -#define GPIO_AFRH9_SHIFT (4) -#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT) -#define GPIO_AFRH10_SHIFT (8) -#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT) -#define GPIO_AFRH11_SHIFT (12) -#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT) -#define GPIO_AFRH12_SHIFT (16) -#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT) -#define GPIO_AFRH13_SHIFT (20) -#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT) -#define GPIO_AFRH14_SHIFT (24) -#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT) -#define GPIO_AFRH15_SHIFT (28) -#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) - -/* GPIO port bit reset register */ - -#define GPIO_BRR_SET(n) (1 << (n)) - -/* GPIO port secure configuration register */ - -#define GPIO_SECCFGR_SET(n) (1 << (n)) - -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H */ diff --git a/arch/arm/src/stm32l5/stm32.h b/arch/arm/src/stm32l5/stm32.h index da1a85b295c..eae700585fc 100644 --- a/arch/arm/src/stm32l5/stm32.h +++ b/arch/arm/src/stm32l5/stm32.h @@ -39,7 +39,7 @@ #include "chip.h" #include "stm32l5_dbgmcu.h" #include "stm32l5_flash.h" -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "stm32l5_pwr.h" #include "stm32l5_rcc.h" #include "stm32l5_spi.h" diff --git a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c index cf5760c43f6..8b1d4c117a1 100644 --- a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c +++ b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c @@ -39,7 +39,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "stm32l5_rcc.h" #ifdef CONFIG_DEBUG_FEATURES diff --git a/arch/arm/src/stm32l5/stm32l5_exti.h b/arch/arm/src/stm32l5/stm32l5_exti.h deleted file mode 100644 index 6ea54c3b1de..00000000000 --- a/arch/arm/src/stm32l5/stm32l5_exti.h +++ /dev/null @@ -1,155 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_exti.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include <nuttx/irq.h> - -#include "chip.h" -#include "hardware/stm32l5_exti.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * pinset - GPIO pin configuration - * risingedge - Enables interrupt on rising edges - * fallingedge - Enables interrupt on falling edges - * event - Generate event when set - * func - When non-NULL, generate interrupt - * arg - Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) is returned on success, otherwise a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); - -/**************************************************************************** - * Name: stm32_exti_alarm - * - * Description: - * Sets/clears EXTI alarm interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg); -#endif - -/**************************************************************************** - * Name: stm32_exti_wakeup - * - * Description: - * Sets/clears EXTI wakeup interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg); -#endif - -/**************************************************************************** - * Name: stm32_exti_comp - * - * Description: - * Sets/clears comparator based events and interrupt triggers. - * - * Input Parameters: - * - cmp: comparator - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) returned on success; a negated errno value is returned on - * failure. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_COMP -int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c deleted file mode 100644 index 0077576be74..00000000000 --- a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c +++ /dev/null @@ -1,186 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_exti_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> -#include <nuttx/irq.h> -#include <nuttx/arch.h> - -#include <stdint.h> -#include <stdbool.h> -#include <assert.h> -#include <errno.h> -#include <nuttx/debug.h> - -#include <arch/irq.h> - -#include "arm_internal.h" -#include "chip.h" -#include "stm32l5_gpio.h" -#include "stm32l5_exti.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct gpio_callback_s -{ - xcpt_t callback; /* Callback entry point */ - void *arg; /* The argument that accompanies the callback */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Interrupt handlers attached to each EXTI */ - -static struct gpio_callback_s g_gpio_handlers[16]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Interrupt Service Routine - Dispatcher - ****************************************************************************/ - -static int stm32_exti0_15_isr(int irq, void *context, void *arg) -{ - int ret = OK; - int exti; - - exti = irq - STM32_IRQ_EXTI0; - DEBUGASSERT((exti >= 0) && (exti <= 15)); - - /* Clear the pending interrupt for both rising and falling edges. */ - - putreg32(0x0001 << exti, STM32_EXTI_RPR1); - putreg32(0x0001 << exti, STM32_EXTI_FPR1); - - /* And dispatch the interrupt to the handler */ - - if (g_gpio_handlers[exti].callback != NULL) - { - xcpt_t callback = g_gpio_handlers[exti].callback; - void *cbarg = g_gpio_handlers[exti].arg; - - ret = callback(irq, context, cbarg); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * pinset - GPIO pin configuration - * risingedge - Enables interrupt on rising edges - * fallingedge - Enables interrupt on falling edges - * event - Generate event when set - * func - When non-NULL, generate interrupt - * arg - Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) is returned on success, otherwise a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg) -{ - uint32_t pin = pinset & GPIO_PIN_MASK; - uint32_t exti = 1 << pin; - int irq = STM32_IRQ_EXTI0 + pin; - int ret; - - g_gpio_handlers[pin].callback = func; - g_gpio_handlers[pin].arg = arg; - - /* Install external interrupt handlers */ - - if (func) - { - irq_attach(irq, stm32_exti0_15_isr, NULL); - up_enable_irq(irq); - } - else - { - /* remove any leftover callback */ - - ret = irq_detach(irq); - if (ret < 0) - { - return ret; - } - - /* disable the interrupt */ - - up_disable_irq(irq); - } - - /* Configure GPIO, enable EXTI line enabled if event or interrupt is - * enabled. - */ - - if (event || func) - { - pinset |= GPIO_EXTI; - } - - stm32_configgpio(pinset); - - /* Configure rising/falling edges */ - - modifyreg32(STM32_EXTI_RTSR1, - risingedge ? 0 : exti, - risingedge ? exti : 0); - modifyreg32(STM32_EXTI_FTSR1, - fallingedge ? 0 : exti, - fallingedge ? exti : 0); - - /* Enable Events and Interrupts */ - - modifyreg32(STM32_EXTI_EMR1, - event ? 0 : exti, - event ? exti : 0); - modifyreg32(STM32_EXTI_IMR1, - func ? 0 : exti, - func ? exti : 0); - - return OK; -} diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.c b/arch/arm/src/stm32l5/stm32l5_gpio.c deleted file mode 100644 index 297a5deb182..00000000000 --- a/arch/arm/src/stm32l5/stm32l5_gpio.c +++ /dev/null @@ -1,408 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include <sys/types.h> -#include <stdint.h> -#include <stdbool.h> -#include <errno.h> -#include <nuttx/debug.h> - -#include <arch/irq.h> -#include <arch/stm32l5/chip.h> -#include <nuttx/spinlock.h> - -#include "arm_internal.h" -#include "chip.h" -#include "stm32l5_gpio.h" - -#include "hardware/stm32l5_syscfg.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static spinlock_t g_configgpio_lock = SP_UNLOCKED; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Base addresses for each GPIO block */ - -const uint32_t g_gpiobase[STM32_NPORTS] = -{ -#if STM32_NPORTS > 0 - STM32_GPIOA_BASE, -#endif -#if STM32_NPORTS > 1 - STM32_GPIOB_BASE, -#endif -#if STM32_NPORTS > 2 - STM32_GPIOC_BASE, -#endif -#if STM32_NPORTS > 3 - STM32_GPIOD_BASE, -#endif -#if STM32_NPORTS > 4 - STM32_GPIOE_BASE, -#endif -#if STM32_NPORTS > 5 - STM32_GPIOF_BASE, -#endif -#if STM32_NPORTS > 6 - STM32_GPIOG_BASE, -#endif -#if STM32_NPORTS > 7 - STM32_GPIOH_BASE, -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_gpioinit - * - * Description: - * Based on configuration within the .config file, it does: - * - Remaps positions of alternative functions. - * - * Typically called from stm32_start(). - * - * Assumptions: - * This function is called early in the initialization sequence so that - * no mutual exclusion is necessary. - * - ****************************************************************************/ - -void stm32_gpioinit(void) -{ -} - -/**************************************************************************** - * Name: stm32_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32_unconfiggpio() with - * the same cfgset first before it can be set to non-alternative function. - * - * Returned Value: - * OK on success - * A negated errno value on invalid port, or when pin is locked as ALT - * function. - * - * To-Do: Auto Power Enable - ****************************************************************************/ - -int stm32_configgpio(uint32_t cfgset) -{ - uintptr_t base; - uint32_t regval; - uint32_t setting; - unsigned int regoffset; - unsigned int port; - unsigned int pin; - unsigned int pos; - unsigned int pinmode; - irqstate_t flags; - - /* Verify that this hardware supports the select GPIO port */ - - port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32_NPORTS) - { - return -EINVAL; - } - - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number and select the port configuration register for that - * pin - */ - - pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - /* Set up the mode register (and remember whether the pin mode) */ - - switch (cfgset & GPIO_MODE_MASK) - { - default: - case GPIO_INPUT: /* Input mode */ - pinmode = GPIO_MODER_INPUT; - break; - - case GPIO_OUTPUT: /* General purpose output mode */ - - /* Set the initial output value */ - - stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); - pinmode = GPIO_MODER_OUTPUT; - break; - - case GPIO_ALT: /* Alternate function mode */ - pinmode = GPIO_MODER_ALT; - break; - - case GPIO_ANALOG: /* Analog mode */ - pinmode = GPIO_MODER_ANALOG; - break; - } - - /* Interrupts must be disabled from here on out so that we have mutually - * exclusive access to all of the GPIO configuration registers. - */ - - flags = spin_lock_irqsave(&g_configgpio_lock); - - /* Now apply the configuration to the mode register */ - - regval = getreg32(base + STM32_GPIO_MODER_OFFSET); - regval &= ~GPIO_MODER_MASK(pin); - regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_MODER_OFFSET); - - /* Set up the pull-up/pull-down configuration (all but analog pins) */ - - setting = GPIO_PUPDR_NONE; - if (pinmode != GPIO_MODER_ANALOG) - { - switch (cfgset & GPIO_PUPD_MASK) - { - default: - case GPIO_FLOAT: /* No pull-up, pull-down */ - break; - - case GPIO_PULLUP: /* Pull-up */ - setting = GPIO_PUPDR_PULLUP; - break; - - case GPIO_PULLDOWN: /* Pull-down */ - setting = GPIO_PUPDR_PULLDOWN; - break; - } - } - - regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); - regval &= ~GPIO_PUPDR_MASK(pin); - regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); - - /* Set the alternate function (Only alternate function pins) */ - - if (pinmode == GPIO_MODER_ALT) - { - setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT; - } - else - { - setting = 0; - } - - if (pin < 8) - { - regoffset = STM32_GPIO_AFRL_OFFSET; - pos = pin; - } - else - { - regoffset = STM32_GPIO_AFRH_OFFSET; - pos = pin - 8; - } - - regval = getreg32(base + regoffset); - regval &= ~GPIO_AFR_MASK(pos); - regval |= (setting << GPIO_AFR_SHIFT(pos)); - putreg32(regval, base + regoffset); - - /* Set speed (Only outputs and alternate function pins) */ - - if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) - { - switch (cfgset & GPIO_SPEED_MASK) - { - default: - case GPIO_SPEED_2MHZ: /* 2 MHz Low speed output */ - setting = GPIO_OSPEED_2MHZ; - break; - - case GPIO_SPEED_25MHZ: /* 25 MHz Medium speed output */ - setting = GPIO_OSPEED_25MHZ; - break; - - case GPIO_SPEED_50MHZ: /* 50 MHz High speed output */ - setting = GPIO_OSPEED_50MHZ; - break; - - case GPIO_SPEED_100MHZ: /* 100 MHz Very High speed output */ - setting = GPIO_OSPEED_100MHZ; - break; - } - } - else - { - setting = 0; - } - - regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); - regval &= ~GPIO_OSPEED_MASK(pin); - regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); - - /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - - regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); - setting = GPIO_OTYPER_OD(pin); - - if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && - (cfgset & GPIO_OPENDRAIN) != 0) - { - regval |= setting; - } - else - { - regval &= ~setting; - } - - putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); - - spin_unlock_irqrestore(&g_configgpio_lock, flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_unconfiggpio - * - * Description: - * Unconfigure a GPIO pin based on bit-encoded description of the pin, set - * it into default HiZ state (and possibly mark it's unused) and unlock it - * whether it was previously selected as alternative function - * (GPIO_ALT|GPIO_CNF_AFPP|...). - * - * This is a safety function and prevents hardware from shocks, as - * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' - * while it should operate in PWM mode could produce excessive on-board - * currents and trigger over-current/alarm function. - * - * Returned Value: - * OK on success - * A negated errno value on invalid port - * - * To-Do: Auto Power Disable - ****************************************************************************/ - -int stm32_unconfiggpio(uint32_t cfgset) -{ - /* Reuse port and pin number and set it to default HiZ INPUT */ - - cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK; - cfgset |= GPIO_INPUT | GPIO_FLOAT; - - /* To-Do: Mark its unuse for automatic power saving options */ - - return stm32_configgpio(cfgset); -} - -/**************************************************************************** - * Name: stm32_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void stm32_gpiowrite(uint32_t pinset, bool value) -{ - uint32_t base; - uint32_t bit; - unsigned int port; - unsigned int pin; - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32_NPORTS) - { - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - /* Set or clear the output on the pin */ - - if (value) - { - bit = GPIO_BSRR_SET(pin); - } - else - { - bit = GPIO_BSRR_RESET(pin); - } - - putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); - } -} - -/**************************************************************************** - * Name: stm32_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool stm32_gpioread(uint32_t pinset) -{ - uint32_t base; - unsigned int port; - unsigned int pin; - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32_NPORTS) - { - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number and return the input state of that pin */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); - } - - return 0; -} diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.h b/arch/arm/src/stm32l5/stm32l5_gpio.h deleted file mode 100644 index b258f8feef1..00000000000 --- a/arch/arm/src/stm32l5/stm32l5_gpio.h +++ /dev/null @@ -1,365 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_gpio.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#ifndef __ASSEMBLY__ -# include <stdint.h> -# include <stdbool.h> -#endif - -#include <nuttx/irq.h> -#include <arch/stm32l5/chip.h> - -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L562XX) -# include "hardware/stm32l5_gpio.h" -#else -# error "Unsupported STM32L5 chip" -#endif - -/**************************************************************************** - * Pre-Processor Declarations - ****************************************************************************/ - -/* Bit-encoded input to stm32_configgpio() */ - -/* Each port bit of the general-purpose I/O (GPIO) ports can be individually - * configured by software in several modes: - * - * - Input floating - * - Input pull-up - * - Input-pull-down - * - Output open-drain with pull-up or pull-down capability - * - Output push-pull with pull-up or pull-down capability - * - Alternate function push-pull with pull-up or pull-down capability - * - Alternate function open-drain with pull-up or pull-down capability - * - Analog - * - * 20-bit Encoding: 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * Inputs: MMUU .... ...X PPPP BBBB - * Outputs: MMUU .... FFOV PPPP BBBB - * Alternate Functions: MMUU AAAA FFO. PPPP BBBB - * Analog: MM.. .... .... PPPP BBBB - */ - -/* Mode: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * MM.. .... .... .... .... - */ - -#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */ -#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) -# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */ -# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */ -# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */ -# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */ - -/* Input/output pull-ups/downs (not used with analog): - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * ..UU .... .... .... .... - */ - -#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */ -#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT) -# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */ -# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */ -# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */ - -/* Alternate Functions: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... AAAA .... .... .... - */ - -#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */ -#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT) -# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT) -# define GPIO_AF0 (0 << GPIO_AF_SHIFT) -# define GPIO_AF1 (1 << GPIO_AF_SHIFT) -# define GPIO_AF2 (2 << GPIO_AF_SHIFT) -# define GPIO_AF3 (3 << GPIO_AF_SHIFT) -# define GPIO_AF4 (4 << GPIO_AF_SHIFT) -# define GPIO_AF5 (5 << GPIO_AF_SHIFT) -# define GPIO_AF6 (6 << GPIO_AF_SHIFT) -# define GPIO_AF7 (7 << GPIO_AF_SHIFT) -# define GPIO_AF8 (8 << GPIO_AF_SHIFT) -# define GPIO_AF9 (9 << GPIO_AF_SHIFT) -# define GPIO_AF10 (10 << GPIO_AF_SHIFT) -# define GPIO_AF11 (11 << GPIO_AF_SHIFT) -# define GPIO_AF12 (12 << GPIO_AF_SHIFT) -# define GPIO_AF13 (13 << GPIO_AF_SHIFT) -# define GPIO_AF14 (14 << GPIO_AF_SHIFT) -# define GPIO_AF15 (15 << GPIO_AF_SHIFT) - -/* Output/Alt function frequency selection: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... FF.. .... .... - */ - -#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */ -#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT) -# define GPIO_SPEED_2MHZ (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ -# define GPIO_SPEED_25MHZ (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */ -# define GPIO_SPEED_50MHZ (2 << GPIO_SPEED_SHIFT) /* 50 MHz High speed output */ -# define GPIO_SPEED_100MHZ (3 << GPIO_SPEED_SHIFT) /* 100 MHz Very High speed output */ - -/* Output/Alt function type selection: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... ..O. .... .... - */ - -#define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */ -#define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */ - -/* If the pin is a GPIO digital output, then this identifies the initial - * output value. If the pin is an input, this bit is overloaded to provide - * the qualifier to distinguish input pull-up and -down: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... ...V .... .... - */ - -#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: If output, initial value of output */ -#define GPIO_OUTPUT_CLEAR (0) - -/* External interrupt selection (GPIO inputs only): - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... ...X .... .... - */ - -#define GPIO_EXTI (1 << 8) /* Bit 8: Configure as EXTI interrupt */ - -/* This identifies the GPIO port: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... .... PPPP .... - */ - -#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ -#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) -# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ -# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ -# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ -# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ -# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ -# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ -# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ -# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ - -/* This identifies the bit in the port: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... .... .... BBBB - */ - -#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO number: 0-15 */ -#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) -# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) -# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) -# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) -# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) -# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) -# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) -# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) -# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) -# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) -# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) -# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) -# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) -# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) -# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) -# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) -# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* Base addresses for each GPIO block */ - -EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32_unconfiggpio() with - * the same cfgset first before it can be set to non-alternative function. - * - * Returned Value: - * OK on success - * ERROR on invalid port, or when pin is locked as ALT function. - * - ****************************************************************************/ - -int stm32_configgpio(uint32_t cfgset); - -/**************************************************************************** - * Name: stm32_unconfiggpio - * - * Description: - * Unconfigure a GPIO pin based on bit-encoded description of the pin, set - * it into default HiZ state (and possibly mark it's unused) and unlock it - * whether it was previously selected as alternative function - * (GPIO_ALT|GPIO_CNF_AFPP|...). - * - * This is a safety function and prevents hardware from shocks, as - * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' - * while it should operate in PWM mode could produce excessive on-board - * currents and trigger over-current/alarm function. - * - * Returned Value: - * OK on success - * ERROR on invalid port - * - ****************************************************************************/ - -int stm32_unconfiggpio(uint32_t cfgset); - -/**************************************************************************** - * Name: stm32_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void stm32_gpiowrite(uint32_t pinset, bool value); - -/**************************************************************************** - * Name: stm32_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool stm32_gpioread(uint32_t pinset); - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * pinset - GPIO pin configuration - * risingedge - Enables interrupt on rising edges - * fallingedge - Enables interrupt on falling edges - * event - Generate event when set - * func - When non-NULL, generate interrupt - * arg - Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) is returned on success, otherwise a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); - -/**************************************************************************** - * Function: stm32_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the provided base address - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_FEATURES -int stm32_dumpgpio(uint32_t pinset, const char *msg); -#else -# define stm32_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Function: stm32_gpioinit - * - * Description: - * Based on configuration within the .config file, it does: - * - Remaps positions of alternative functions. - * - * Typically called from stm32_start(). - * - ****************************************************************************/ - -void stm32_gpioinit(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.c b/arch/arm/src/stm32l5/stm32l5_lowputc.c index d10ce831abf..b9b91bddc02 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.c +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.c @@ -35,7 +35,7 @@ #include "stm32.h" #include "stm32l5_rcc.h" -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "stm32l5_uart.h" /**************************************************************************** diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index b4bf654fda8..37a219f8b47 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -50,7 +50,7 @@ #include <arch/board/board.h> #include "chip.h" -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "stm32l5_uart.h" #ifdef SERIAL_HAVE_DMA # include "stm32l5_dma.h" diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index 87c822ee87a..5e08abc7a37 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -75,7 +75,7 @@ #include "arm_internal.h" #include "chip.h" #include "stm32.h" -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #ifdef CONFIG_STM32_SPI_DMA # include "stm32l5_dma.h" #endif diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c index 45d63d4f1b6..a3200936e06 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.c +++ b/arch/arm/src/stm32l5/stm32l5_start.c @@ -37,7 +37,7 @@ #include "nvic.h" #include "stm32.h" -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "stm32l5_userspace.h" #include "stm32l5_start.h" diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index 7352fc82277..4e31b52501a 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -41,7 +41,7 @@ #include "chip.h" #include "arm_internal.h" #include "stm32.h" -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "stm32l5_tim.h" /**************************************************************************** diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h b/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h index 847c837138c..ac322b4f505 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h +++ b/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h @@ -31,7 +31,7 @@ #include <nuttx/compiler.h> #include <stdint.h> -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c index f27e0286dd9..a64b0cfd9aa 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "nucleo-l552ze.h" #include <arch/board/board.h> diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c index 7ba2e3c8fab..995f6645aa6 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c @@ -33,7 +33,7 @@ #include "arm_internal.h" #include "nucleo-l552ze.h" #include "stm32l5_pwr.h" -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include <arch/board/board.h> diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c index 429c818dd11..6e2e47224e8 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c @@ -33,7 +33,7 @@ #include <nuttx/arch.h> #include <nuttx/board.h> -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "nucleo-l552ze.h" #include <arch/board/board.h> diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c index 8318cb30f2c..616962c59e1 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c @@ -34,7 +34,7 @@ #include <nuttx/board.h> #include <arch/board/board.h> -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "nucleo-l552ze.h" #ifndef CONFIG_ARCH_LEDS diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c index 4d3dd824946..9419d7506bd 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "stm32l562e-dk.h" #include <arch/board/board.h> diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c index 3091f179081..a51c676290e 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c @@ -33,7 +33,7 @@ #include <nuttx/arch.h> #include <nuttx/board.h> -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "stm32l562e-dk.h" #include <arch/board/board.h> diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c index fa01c257261..06018f8d95d 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c @@ -34,7 +34,7 @@ #include <nuttx/board.h> #include <arch/board/board.h> -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" #include "stm32l562e-dk.h" #ifndef CONFIG_ARCH_LEDS diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h b/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h index 1352d9c3d8f..fa9e73b84e2 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h @@ -31,7 +31,7 @@ #include <nuttx/compiler.h> #include <stdint.h> -#include "stm32l5_gpio.h" +#include "stm32_gpio.h" /**************************************************************************** * Pre-processor Definitions
