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The following commit(s) were added to refs/heads/master by this push:
new c7080cbdfeb arch/arm/imxrt: Small cleanups for OCOTP headers
c7080cbdfeb is described below
commit c7080cbdfebaecf27c7325e7c7bfee9353b9eefa
Author: Jukka Laitinen <[email protected]>
AuthorDate: Tue Sep 22 11:08:38 2026 +0300
arch/arm/imxrt: Small cleanups for OCOTP headers
- Add conditional includes for both 117x/118x headers in
hardware/imxrt_ocotp.h
- Add CHIP_ID and UNIQUE_ID addresses in imxrt118x_ocotp.h
- Remove access to those timing registers which don't exist on imxrt117x,
which don't exist on that chip, in imxrt_ocotp_initialize.
Signed-off-by: Jukka Laitinen <[email protected]>
---
arch/arm/src/imxrt/hardware/imxrt_ocotp.h | 13 ++++---------
arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h | 3 ++-
arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h | 6 ++++++
arch/arm/src/imxrt/imxrt_ocotp.c | 4 ++++
4 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/arch/arm/src/imxrt/hardware/imxrt_ocotp.h
b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h
index 18dda8053ab..5d562ad1755 100644
--- a/arch/arm/src/imxrt/hardware/imxrt_ocotp.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h
@@ -36,15 +36,10 @@
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
-#ifdef CONFIG_ARCH_FAMILY_IMXRT118x
-
-/* On chips fronted by the EdgeLock Enclave (e.g. RT1180) the OCOTP
- * register layout differs and only a shadow-read window is exposed to
- * the SoC; see hardware/rt118x/imxrt118x_ocotp.h for details.
- */
-
+#if defined(CONFIG_ARCH_FAMILY_IMXRT117x)
+# include "hardware/rt117x/imxrt117x_ocotp.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x)
# include "hardware/rt118x/imxrt118x_ocotp.h"
-
#else
/****************************************************************************
@@ -436,6 +431,6 @@
#define OCOTP_LOCK_FIELD_RETURN_MASK (15 <<
OCOTP_LOCK_FIELD_RETURN_SHIFT)
# define OCOTP_LOCK_FIELD_RETURN(n) ((uint32_t)(n) <<
OCOTP_LOCK_FIELD_RETURN_SHIFT)
-#endif /* CONFIG_ARCH_FAMILY_IMXRT118x */
+#endif /* CONFIG_ARCH_FAMILY_IMXRT117x / CONFIG_ARCH_FAMILY_IMXRT118x */
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_OCOTP_H */
diff --git a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h
b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h
index 9b1d1973995..bfb46a424c0 100644
--- a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h
+++ b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ocotp.h
@@ -68,6 +68,7 @@
#define IMXRT_OCOTP_READ_FUSE_DATA1 (IMXRT_OCOTP_BASE +
IMXRT_OCOTP_READ_FUSE_DATA1_OFFSET)
#define IMXRT_OCOTP_READ_FUSE_DATA2 (IMXRT_OCOTP_BASE +
IMXRT_OCOTP_READ_FUSE_DATA2_OFFSET)
#define IMXRT_OCOTP_READ_FUSE_DATA3 (IMXRT_OCOTP_BASE +
IMXRT_OCOTP_READ_FUSE_DATA3_OFFSET)
+#define IMXRT_OCOTP_READ_FUSE_DATA IMXRT_OCOTP_READ_FUSE_DATA0
#define IMXRT_OCOTP_SW_LOCK (IMXRT_OCOTP_BASE +
IMXRT_OCOTP_SW_LOCK_OFFSET)
#define IMXRT_OCOTP_BIT_LOCK (IMXRT_OCOTP_BASE +
IMXRT_OCOTP_BIT_LOCK_OFFSET)
#define IMXRT_OCOTP_LOCKED0 (IMXRT_OCOTP_BASE +
IMXRT_OCOTP_LOCKED0_OFFSET)
@@ -101,7 +102,7 @@
#define OCOTP_CTRL_WORDLOCK (1 << 15) /* Bit 15: Lock fuse word */
#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16) /* Bits 16-32: Write unlock */
#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF << OCOTP_CTRL_WR_UNLOCK_SHIFT)
-#define OCOTP_CTRL_WR_UNLOCK(n) (((n) << OCOTP_CTRL_WR_UNLOCK_SHIFT) &
OCOTP_CTRL_WR_UNLOCK_MASK)
+#define OCOTP_CTRL_WR_UNLOCK (0x3E77 << OCOTP_CTRL_WR_UNLOCK_SHIFT)
/* OTP Controller Control and Status Register (CTRL_SET) */
#define OCOTP_CTRL_SET_ADDR_SHIFT (0) /* Bits 0-10: OTP write and
read access address register */
diff --git a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h
b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h
index 8ddd178799c..09d288ab485 100644
--- a/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h
+++ b/arch/arm/src/imxrt/hardware/rt118x/imxrt118x_ocotp.h
@@ -44,4 +44,10 @@
#define IMXRT_OCOTP_SHADOW_BASE (0x47518000ul)
+#define IMXRT_OCOTP_CHIP_ID (IMXRT_OCOTP_SHADOW_BASE + 0x54)
+#define IMXRT_OCOTP_CHIP_ID_SHIFT 9
+#define IMXRT_OCOTP_CHIP_ID_MASK 0x7fffff
+#define IMXRT_OCOTP_UNIQUE_ID_MSB (IMXRT_OCOTP_SHADOW_BASE + 0xc0)
+#define IMXRT_OCOTP_UNIQUE_ID_LSB (IMXRT_OCOTP_SHADOW_BASE + 0xc4)
+
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_OCOTP_H */
diff --git a/arch/arm/src/imxrt/imxrt_ocotp.c b/arch/arm/src/imxrt/imxrt_ocotp.c
index 24ac4b716d9..9de9f5b9957 100644
--- a/arch/arm/src/imxrt/imxrt_ocotp.c
+++ b/arch/arm/src/imxrt/imxrt_ocotp.c
@@ -66,6 +66,7 @@ static inline void imxrt_ocotp_reset_errors(void)
static void imxrt_ocotp_initialize(void)
{
static bool once = false;
+#ifndef CONFIG_ARCH_FAMILY_IMXRT117x
uint32_t read;
uint32_t prog;
uint32_t relax;
@@ -74,6 +75,7 @@ static void imxrt_ocotp_initialize(void)
uint32_t wait;
const uint32_t ipg_freq_hz = BOARD_CPU_FREQUENCY / IMXRT_IPG_PODF_DIVIDER;
+#endif
if (!once)
{
@@ -81,6 +83,7 @@ static void imxrt_ocotp_initialize(void)
imxrt_clockall_ocotp_ctrl();
+#ifndef CONFIG_ARCH_FAMILY_IMXRT117x
/* WAIT specifies time interval between auto read and write
* access in one time program.
*
@@ -169,6 +172,7 @@ static void imxrt_ocotp_initialize(void)
OCOTP_TIMING2_RELAX_PROG_MASK,
OCOTP_TIMING2_RELAX_READ(relax_read) |
OCOTP_TIMING2_RELAX_PROG(relax_prog));
+#endif
}
}
