methodmissing opened a new pull request, #20523:
URL: https://github.com/apache/nuttx/pull/20523
## Summary
The i.MX RT1176 pairs the Cortex-M7 with a Cortex-M4 that the NuttX port
leaves in ROM-held reset.
This adds an RPTUN backend (`CONFIG_IMXRT_RPTUN`) so NuttX on the CM7 runs
the CM4 as an RPTUN
remote: the loader writes the CM4 ELF through the LMEM backdoor window, the
boot vector goes into
`IOMUXC_LPSR_GPR0/1` as the backdoor alias of the code TCM (the CM4-native
address does not boot,
which NXP's MCMGR also assumes), SRC releases the core, and virtqueue kicks
travel on MU-A channel 0
with coalescing in the mailbox. `SRC_SRMR` is set so a CM4 lockup resets
only the CM4. A released
slice cannot be held in reset again, so stop parks the core in a `wfi` loop
written over the image
start and the next start reloads the image. The board passes name, ELF path,
address environment,
boot vector and autostart to `imxrt_rptun_init()` and maps the shared window
non-cacheable.
The option is offered only on parts with a CM4 (`IMXRT_HAVE_CM4`, selected
by the MIMXRT1176) and
selects `DEV_SIMPLE_ADDRENV` for libmetal. The CM4 image provides the
resource table, including a
carveout resource for the shared window that this rptun places vrings and
buffers in; the remote may
be bare metal. Three commits: the backend with the MU and SRC register
headers, the platform
documentation, and a `fmu-v6xrt:rptun` configuration on the Pixhawk 6X-RT as
the in-tree user,
with the CM4 image loaded from the SD card or, with
`CONFIG_FMU_V6XRT_CM4_ROMFS`, baked into the
etc ROMFS.
Related: apache/nuttx#TBD starts the DWT cycle counter on imxrt so `rpmsg
ping` reports times;
independent, cherry-picked for the timing figures below. The same backend is
in use by the PX4
`px4_fmu-v6xrt` rpmsg variant on the PX4/NuttX 12.12 fork (PX4/NuttX#420).
## Impact
* New feature: YES. Existing feature changed: NO.
* User: NO unless enabled; then the board calls `imxrt_rptun_init()` and
supplies a CM4 image.
* Build: NO for existing configurations. Hardware: MIMXRT1176 only; new
files plus MU clock-gate
macros.
* Documentation: YES, platform page section and the board page, included.
Security: the CM4 is a
second bus master, its firmware owns containment; the host accepts no
address outside the window
it mapped.
* Compatibility: NO changes.
## Testing
* Host: macOS, GNU Arm Embedded 9-2020-q2 (gcc 9.3.1), standalone
`tools/configure.sh -l
fmu-v6xrt:rptun && make` against this branch with apache/nuttx-apps master.
* Target: Pixhawk 6X-RT (i.MX RT1176 rB0), image flashed through the PX4
bootloader, stock nsh
over USB CDC/ACM, a 4 KB bare-metal CM4 remote with the resource table and
carveout baked into
the etc ROMFS.
* `tools/checkpatch.sh` passes on all three commits.
Logs after change (new feature, none before), run of 2026-10-08. `xd
0x2021fff0` reads the CM4
status block through the window: `0xC0DE0003` is rpmsg ready, then IPSR,
kicks received and
messages sent. After `rptun stop` the slice status reads reset-by-software
and the image start
holds the park loop (SP, reset vector, `wfi; b .-2`); the second start and
ping show the reload.
```
NuttShell (NSH) NuttX-13.1.0
nsh> rptun start /dev/rptun/cm4
nsh> xd 0x2021fff0 16
Hex dump:
0000: 03 00 de c0 00 00 00 00 06 00 00 00 03 00 00 00 ................
nsh> rpmsg ping /dev/rpmsg/cm4 100 64 3 0
nsh> dmesg
ping times: 100
buffer_len: 1008, send_len: 64
avg: 0 s, 18208 ns
min: 0 s, 16215 ns
max: 0 s, 47375 ns
rate: 28.119507 Mbits/sec
nsh> rptun stop /dev/rptun/cm4
nsh> mw 0x40c04290
0x40c04290 = 0x00000008
nsh> xd 0x20200000 12
Hex dump:
0000: 00 00 02 20 09 00 20 20 30 bf fd e7 ... .. 0...
nsh> rptun start /dev/rptun/cm4
nsh> rpmsg ping /dev/rpmsg/cm4 10 64 3 0
nsh> dmesg
ping times: 10
buffer_len: 1008, send_len: 64
avg: 0 s, 20281 ns
min: 0 s, 16091 ns
max: 0 s, 44095 ns
rate: 25.245303 Mbits/sec
```
Fault containment (CM4 hard fault, lockup, hang, and malformed lengths from
the remote) was
exercised with the same backend on the PX4/NuttX 12.12 fork, logs in
PX4/NuttX#420; the CM7 stayed
up through every case and `SRC_SRSR` recorded no chip reset.
## PR verification Self-Check
* [x] This PR introduces only one functional change.
* [x] I have updated all required description fields above.
* [x] My PR adheres to Contributing Guidelines and Documentation.
* [ ] My PR is still work in progress (not ready for review).
* [x] My PR is ready for review and can be safely merged into a codebase.
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