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new 081e55461eb arch/xtensa/esp32s3: Make SPI CS, MOSI and MISO pins
signed.
081e55461eb is described below
commit 081e55461eb32337bab13c21a16f8c2524e86e2d
Author: Zhaoqi Xu <[email protected]>
AuthorDate: Tue Oct 6 08:56:14 2026 +0800
arch/xtensa/esp32s3: Make SPI CS, MOSI and MISO pins signed.
The CS, MOSI and MISO pins can be set to -1 in Kconfig when the board
does not use them, and esp32s3_spi_init() skips a pin when it is
negative. The pins are stored as uint8_t in esp32s3_spi_config_s, so
-1 becomes 255, every "pin >= 0" check is always true, and 255 is
passed to esp_gpiowrite() and esp_configgpio(), which trips their
DEBUGASSERT.
Store these three pins as int8_t so -1 is kept and the existing checks
work.
Fixes apache/nuttx#20186
Assisted-by: Grok Bot
Signed-off-by: Zhaoqi Xu <[email protected]>
---
arch/xtensa/src/esp32s3/esp32s3_spi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/esp32s3_spi.c
b/arch/xtensa/src/esp32s3/esp32s3_spi.c
index 86353bf8aaf..8482b59aa0a 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_spi.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_spi.c
@@ -124,9 +124,9 @@ struct esp32s3_spi_config_s
enum spi_mode_e mode; /* SPI default mode */
uint8_t id; /* ESP32-S3 SPI device ID: SPIx {2,3} */
- uint8_t cs_pin; /* GPIO configuration for CS */
- uint8_t mosi_pin; /* GPIO configuration for MOSI */
- uint8_t miso_pin; /* GPIO configuration for MISO */
+ int8_t cs_pin; /* GPIO configuration for CS */
+ int8_t mosi_pin; /* GPIO configuration for MOSI */
+ int8_t miso_pin; /* GPIO configuration for MISO */
uint8_t clk_pin; /* GPIO configuration for CLK */
#ifdef CONFIG_ESP32S3_SPI_DMA
uint8_t periph; /* Peripheral ID */
