dcgong2917 opened a new pull request, #20612:
URL: https://github.com/apache/nuttx/pull/20612
## Summary
Exposes the two RTL8730E (AmebaSmart CA32) SPI controllers through the shared
Ameba SPI driver at `/dev/spiN`, gated by `CONFIG_AMEBA_SPI` (default
disabled). No common driver code changes -- everything chip-specific goes in
the new `ameba_spi_chip.h`, so the other Ameba ICs are untouched.
Three amebasmart-specific differences worth calling out:
* The APB function and clock masks are **not equal** on this chip (SPI0
function bit9 / clock bit8, SPI1 function bit10 / clock bit9), unlike the
other Ameba peripherals where one value serves both.
* The master-role bits live in `REG_HSYS_HPLAT_CTRL` (bit 25/26), not in the
`REG_LSYS_PLAT_CTRL` of the KM4-based parts.
* The register bases must be the non-secure aliases: `SSI_SetRole()`
identifies the controller by pointer-comparing against the fwlib's own
`SPI0_DEV`, so a secure alias would set SPI1's master bit when asked for
SPI0.
The SSI IP clock is read at run time from the PLL and HS_AHB dividers rather
than tabulated, mirroring the SDK's own `spi_get_ipclk()`.
## Impact
New peripheral driver for one board, disabled by default. No change to any
shared driver, nor to any other chip or board.
## Testing
Hardware: RTL8730E EVB, MOSI/MISO loopback, both buses registered at once
(SPI0 on PB18-PB21, SPI1 on PA9-PA12).
The IP-clock computation was cross-checked against the hardware registers:
`DIVN_SDM=21` → 920 MHz NP_PLL, `CKD_HBUS=8` → 102.2 MHz ip_clk, consistent
with the `SPI_BAUDR` value the driver programmed.
Build: `rtl8730e_evb:spi` plus the existing `nsh`/`i2c`/`gpio`/`uart`
configs, each with both the make and cmake build systems; checkpatch clean;
defconfig matches `savedefconfig`.
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