avgoor commented on issue #16133:
URL: https://github.com/apache/nuttx/issues/16133#issuecomment-6247629090
Something has changed recently and now it gets stuck even on `smp` tests:
```
(gdb) where
#0 0x10002b06 in spin_lock_notrace (lock=0x20002bc4 <g_cpu_irqlock>)
at nuttx/include/nuttx/spinlock.h:146
#1 0x10002bc2 in enter_critical_section_notrace () at irq/irq_csection.c:183
#2 0x10025400 in wd_expiration (ticks=11802) at wdog/wd_start.c:115
#3 0x1002559c in wd_timer (ticks=11802) at wdog/wd_start.c:362
#4 0x10022b10 in nxsched_process_timer () at sched/sched_processtick.c:192
#5 0x10010a18 in rp23xx_timerisr (irq=15, regs=0x0, arg=0x0) at
chip/rp23xx_timerisr.c:90
#6 0x10002a00 in irq_dispatch (irq=15, context=0x0) at
irq/irq_dispatch.c:143
#7 0x10001b86 in exception_direct () at armv8-m/arm_doirq.c:63
#8 <signal handler called>
#9 __aeabi_ldivmod () at
/build/arm-none-eabi-gcc/src/gcc-16.2.0/libgcc/config/arm/bpabi.S:189
#10 0x100061e4 in clock_systime_timespec (ts=0x20006ac8) at
clock/clock_systime_timespec.c:84
#11 0x10021eea in nxclock_gettime (clock_id=1, tp=0x20006ac8) at
clock/clock_gettime.c:107
#12 0x10021f90 in clock_gettime (clock_id=1, tp=0x20006ac8) at
clock/clock_gettime.c:215
#13 0x1002ac60 in hog_milliseconds (milliseconds=100) at smp_main.c:99
#14 0x1002ad9a in hog_time (caller=0x100500a4 "Thread", threadno=1) at
smp_main.c:132
#15 0x1002adde in barrier_thread (parameter=0x1) at smp_main.c:156
#16 0x100301a0 in pthread_startup (entry=0x1002adbd <barrier_thread>,
arg=0x1)
at pthread/pthread_create.c:65
#17 0x10031e9c in pthread_start () at pthread/pthread_create.c:146
#18 0x00000000 in ?? ()
(gdb) inf thr
Id Target Id
Frame
* 1 Thread 1 "rp2350.dap.core0" (Name: rp2350.dap.core0, state:
debug-request) 0x10002b06 in spin_lock_notrace (lock=0x20002bc4 <g_cpu_irqlock>)
at nuttx/include/nuttx/spinlock.h:146
2 Thread 2 "rp2350.dap.core1" (Name: rp2350.dap.core1, state:
debug-request) 0x10002b06 in spin_lock_notrace (lock=0x20002bc4 <g_cpu_irqlock>)
at nuttx/include/nuttx/spinlock.h:146
(gdb)
```
But RISC-V implementation seems to be OK, this is something ARM
implementation specific.
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