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The following commit(s) were added to refs/heads/master by this push:
new 54b883cff14 boards/risc-v/gd32vw553k-start: fix the I2C1 pins and the
board docs
54b883cff14 is described below
commit 54b883cff1401d1cd97923a81b8521dadbd45c5f
Author: Jorge Guzman <[email protected]>
AuthorDate: Sun Oct 18 09:34:32 2026 -0300
boards/risc-v/gd32vw553k-start: fix the I2C1 pins and the board docs
I2C1 is on PB15 (SCL) / PA8 (SDA), not PB12/PB13, which the QFN32 package
does not have. Register /dev/i2c1 and drop I2C1 from periph, where those
pins are the I2C0 fallback.
Document the J4 caps, the J5 console jumpers and flashing with a J-Link.
Tested on hardware with the sht3x configuration plus I2C1.
Signed-off-by: Jorge Guzman <[email protected]>
---
.../gd32vw55x/boards/gd32vw553k-start/index.rst | 33 ++++++++++++++++------
.../gd32vw553k-start/configs/periph/defconfig | 1 -
.../gd32vw55x/gd32vw553k-start/include/board.h | 13 +++++++--
.../gd32vw55x/gd32vw553k-start/src/gd32_bringup.c | 21 +++++++++++++-
4 files changed, 55 insertions(+), 13 deletions(-)
diff --git
a/Documentation/platforms/risc-v/gd32vw55x/boards/gd32vw553k-start/index.rst
b/Documentation/platforms/risc-v/gd32vw55x/boards/gd32vw553k-start/index.rst
index 102fe33829b..4e30e8de3d1 100644
--- a/Documentation/platforms/risc-v/gd32vw55x/boards/gd32vw553k-start/index.rst
+++ b/Documentation/platforms/risc-v/gd32vw55x/boards/gd32vw553k-start/index.rst
@@ -22,14 +22,17 @@ Features
- On-board GD-Link probe: SWD/JTAG plus a USB CDC virtual COM port, both
over the single USB Type-C connector
- Two test pin headers (J1, J2) breaking out the GPIOs
-- BOOT0/BOOT1 jumpers, a power jumper and a reset button (NRST)
+- BOOT0/BOOT1 jumpers, a power jumper, the J5 jumpers that route the console
+ UART to the GD-Link virtual COM port, and a reset button (NRST); there is no
+ user button
- Three user LEDs (red, green, blue)
Serial Console
==============
The console is UART2 (PA6 TX / PA7 RX), wired to the GD-Link virtual COM port.
-It shows up on the host as ``/dev/ttyACM0`` at 115200 8N1.
+It shows up on the host as ``/dev/ttyACM0`` at 115200 8N1. The J5 jumpers must
+be in place for the UART to reach the probe.
LEDs
====
@@ -98,20 +101,31 @@ is a plain GPIO. The silkscreen abbreviates the port
letter (``A0`` is PA0,
======== =================== ======== ===================
.. note::
- PA13/PA14/PA15/PB3/PB4 on J2 are the chip's JTAG pins, wired to the on-board
- GD-Link through the J4 shorting caps. Use them as plain GPIO only after
- removing those caps, or the debug probe and the application will fight over
- the lines.
+ PA13/PA14/PA15/PB3 on J2 are the chip's JTAG pins (JTMS, JTCK, JTDI, JTDO),
+ wired to the on-board GD-Link through the J4 shorting caps. Keep the J4
+ caps closed to flash and debug through the GD-Link. To use an external
+ probe such as a SEGGER J-Link, or to use those pins as plain GPIO, remove
+ the caps first, or the GD-Link and the other user will fight over the
+ lines. PB4 (JNTRST) drives LED3.
Flashing
========
-The board is programmed with OpenOCD through the GD-Link probe. The GigaDevice
-OpenOCD fork (shipped with the vendor SDK) is required::
+The board is programmed with OpenOCD through the on-board GD-Link probe, with
+the J4 caps closed. The GigaDevice OpenOCD fork (shipped with the vendor SDK)
+is required::
$ openocd -f openocd_gdlink.cfg \
-c "program nuttx.bin 0x08000000 verify reset exit"
+To use an external programmer instead, a SEGGER J-Link works: remove the J4
+caps and wire it to J2 (VTref to +3V3, TMS to PA13, TCK to PA14, TDI to PA15,
+TDO to PB3, and GND). With a command file holding
+``loadbin nuttx.bin, 0x08000000``, ``r`` and ``g``::
+
+ $ JLinkExe -nogui 1 -device GD32VW553KMQ7 -if JTAG -JTAGConf -1,-1 \
+ -speed 4000 -autoconnect 1 -CommandFile flash.jlink
+
NuttX is linked at 0x08000000, bypassing the vendor MBL bootloader.
.. note::
@@ -210,7 +224,8 @@ driver -- a small example to validate the I2C master port
against a real
device. Because SPI is *off* here, I2C0 is routed to the J1 header on
**PA2 (SCL)** and **PA3 (SDA)** (adjacent pins on the second row of J1, both
AF4); with SPI on (the ``periph`` case) it falls back to PB15 (SCL, J1) and
-PA8 (SDA, J2). See the pin-header tables above.
+PA8 (SDA, J2). I2C1, when enabled, uses the same PB15/PA8 pair (AF6), so it
+cannot be combined with that fallback. See the pin-header tables above.
Wire the sensor to J1: SCL -> PA2, SDA -> PA3, VCC -> +3V3 (J2) or the module
3.3 V, GND -> GND. A breakout with its own pull-ups is assumed; the pins are
diff --git a/boards/risc-v/gd32vw55x/gd32vw553k-start/configs/periph/defconfig
b/boards/risc-v/gd32vw55x/gd32vw553k-start/configs/periph/defconfig
index 66a930475f7..2678e5c0987 100644
--- a/boards/risc-v/gd32vw55x/gd32vw553k-start/configs/periph/defconfig
+++ b/boards/risc-v/gd32vw55x/gd32vw553k-start/configs/periph/defconfig
@@ -31,7 +31,6 @@ CONFIG_GD32VW55X_DMA=y
CONFIG_GD32VW55X_FWDGT=y
CONFIG_GD32VW55X_GPIO_IRQ=y
CONFIG_GD32VW55X_I2C0=y
-CONFIG_GD32VW55X_I2C1=y
CONFIG_GD32VW55X_PROGMEM=y
CONFIG_GD32VW55X_PWM=y
CONFIG_GD32VW55X_RNG=y
diff --git a/boards/risc-v/gd32vw55x/gd32vw553k-start/include/board.h
b/boards/risc-v/gd32vw55x/gd32vw553k-start/include/board.h
index aa792d795b9..0372b044606 100644
--- a/boards/risc-v/gd32vw55x/gd32vw553k-start/include/board.h
+++ b/boards/risc-v/gd32vw55x/gd32vw553k-start/include/board.h
@@ -99,9 +99,18 @@
# endif
#endif
+/* I2C1 uses PB15 (SCL) / PA8 (SDA) on AF6, on the J1/J2 headers. The
+ * QFN32 package has no PB12/PB13, and the other I2C1 options are the
+ * console or JTAG pins. PB15/PA8 are also the I2C0 fallback (SPI on) and
+ * the UART1/USART0 pins, so only one of them can be enabled.
+ */
+
#ifdef CONFIG_GD32VW55X_I2C1
-# define GPIO_I2C1_SCL GPIO_I2C1_SCL_4 /* PB12, AF6 */
-# define GPIO_I2C1_SDA GPIO_I2C1_SDA_4 /* PB13, AF6 */
+# if defined(CONFIG_GD32VW55X_I2C0) && defined(CONFIG_GD32VW55X_SPI)
+# error "I2C1 and the I2C0 fallback (SPI on) both need PB15/PA8"
+# endif
+# define GPIO_I2C1_SCL GPIO_I2C1_SCL_5 /* PB15, AF6 (J1) */
+# define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PA8, AF6 (J2) */
#endif
/* PWM. The board bringup registers /dev/pwm0 on TIMER1. Route its channel
diff --git a/boards/risc-v/gd32vw55x/gd32vw553k-start/src/gd32_bringup.c
b/boards/risc-v/gd32vw55x/gd32vw553k-start/src/gd32_bringup.c
index b4fdc2e830c..c5acea0b0b2 100644
--- a/boards/risc-v/gd32vw55x/gd32vw553k-start/src/gd32_bringup.c
+++ b/boards/risc-v/gd32vw55x/gd32vw553k-start/src/gd32_bringup.c
@@ -94,7 +94,7 @@ int gd32_ble_initialize(void);
int gd32_bringup(void)
{
-#ifdef CONFIG_GD32VW55X_I2C0
+#if defined(CONFIG_GD32VW55X_I2C0) || defined(CONFIG_GD32VW55X_I2C1)
struct i2c_master_s *i2c;
#endif
#ifdef CONFIG_GD32VW55X_SPI
@@ -177,6 +177,25 @@ int gd32_bringup(void)
}
#endif
+#ifdef CONFIG_GD32VW55X_I2C1
+ i2c = gd32_i2cbus_initialize(1);
+ if (i2c == NULL)
+ {
+ ferr("ERROR: failed to initialize I2C1\n");
+ }
+ else
+ {
+#ifdef CONFIG_I2C_DRIVER
+ /* Expose the bus as /dev/i2c1 for the i2ctool */
+
+ if (i2c_register(i2c, 1) < 0)
+ {
+ ferr("ERROR: failed to register /dev/i2c1\n");
+ }
+#endif
+ }
+#endif
+
#ifdef CONFIG_GD32VW55X_SPI
/* The family has a single SPI instance: bus 0. Configure the chip select
* GPIOs first, then bring the bus up.
