casaroli commented on code in PR #20723: URL: https://github.com/apache/nuttx/pull/20723#discussion_r4313506576
########## arch/arm64/include/irq.h: ########## @@ -154,7 +154,7 @@ #define REG_SP_EL0 (34) #define REG_EXE_DEPTH (35) #define REG_SCTLR_EL1 (36) -#define REG_RESERVED (37) +#define REG_TPIDR_EL0 (37) Review Comment: Thank you. I tried #20801 on `qemu-armv8a:knsh` (QEMU with HVF). It also fixes code on a `makecontext()` stack, but I found two problems: 1. In #20801 the kernel also reads `TPIDR_EL0` in `tls_get_info()`, and user code can write that register. A program that sets `TPIDR_EL0` to an address of its choice and then calls `open()` on a missing file makes the kernel write `ENOENT` to that address. With `CONFIG_TLS_NCLEANUP > 0` the kernel also writes a callback and its argument there. In this PR only user code reads `TPIDR_EL0`; the kernel still gets the TLS info from the TCB. 2. The kernel writes `stack_alloc_ptr` to `TPIDR_EL0` at each context switch, so a value that user code writes is lost (test: write it, yield 20 times, read back: the old value). Native TLS needs a thread pointer that the program sets, because each separately linked program has its own TLS block. risc-v (`REG_TP`), xtensa (`REG_THREADPTR`) and x86_64 (`REG_FSBASE`) keep the thread pointer in the context for this reason. The register uses slot 37, which was padding before, so the context size does not change. The cost is 4 instructions per exception. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
