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new 7e652be44d2 arch/arm: remove undefined CONFIG_SPI_DMAPRIO references
7e652be44d2 is described below
commit 7e652be44d2a04a88201cab91f089aab3448552b
Author: Swatantra Yadav <[email protected]>
AuthorDate: Sun Oct 18 18:48:27 2026 +0530
arch/arm: remove undefined CONFIG_SPI_DMAPRIO references
As identified in issue #11932, CONFIG_SPI_DMAPRIO was an artifact cloned
from the SDIO driver into STM32 SPI in 2012, but was never defined in
any Kconfig file. Subsequent ARM SPI drivers (STM32 variants and AT32)
copied the block verbatim, leaving dead #if defined(CONFIG_SPI_DMAPRIO)
checks and dead #error "Illegal value for CONFIG_SPI_DMAPRIO"
directives.
Because CONFIG_SPI_DMAPRIO was never defined in Kconfig, drivers always
fell back to the default DMA priorities (e.g., DMA_CCR_PRIMED or
DMA_SCR_PRILO).
This patch removes the dead #if checks and dead #error directives across
all 14 affected SPI and I2S driver files, directly assigning the
appropriate default DMA priority. Also fixes a missing closing
parenthesis in stm32wl5_spi.c.
Fixes #11932.
Signed-off-by: Swatantra Yadav <[email protected]>
---
arch/arm/src/at32/at32_spi.c | 161 +++++++++++-----------
arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c | 63 ++++-----
arch/arm/src/common/stm32/stm32_spi_m0_v1.c | 137 +++++++++---------
arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c | 118 ++++++++--------
arch/arm/src/stm32f7/stm32_i2s.c | 55 ++++----
arch/arm/src/stm32f7/stm32_spi.c | 97 +++++++------
arch/arm/src/stm32h5/stm32_spi.c | 131 +++++++++---------
arch/arm/src/stm32h7/stm32_spi.c | 126 +++++++++--------
arch/arm/src/stm32h7/stm32_spi_slave.c | 113 ++++++++-------
arch/arm/src/stm32l4/stm32l4_spi.c | 113 +++++++--------
arch/arm/src/stm32l5/stm32l5_spi.c | 12 +-
arch/arm/src/stm32u5/stm32_spi.c | 126 +++++++++--------
arch/arm/src/stm32wb/stm32wb_spi.c | 27 ++--
arch/arm/src/stm32wl5/stm32wl5_spi.c | 73 +++++-----
14 files changed, 636 insertions(+), 716 deletions(-)
diff --git a/arch/arm/src/at32/at32_spi.c b/arch/arm/src/at32/at32_spi.c
index bc36f114339..4ead075752f 100644
--- a/arch/arm/src/at32/at32_spi.c
+++ b/arch/arm/src/at32/at32_spi.c
@@ -72,18 +72,8 @@
#ifdef CONFIG_AT32_SPI_DMA
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# elif defined(CONFIG_AT32_AT32F43XX)
-# define SPI_DMA_PRIO DMA_CCR_PRIMED
-# else
-# error "Unknown AT32 DMA"
-# endif
-
# if defined(CONFIG_AT32_AT32F43XX)
-# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
+# define SPI_DMA_PRIO DMA_CCR_PRIMED
# else
# error "Unknown AT32 DMA"
# endif
@@ -914,10 +904,11 @@ static inline void spi_dmatxstart(struct at32_spidev_s
*priv)
****************************************************************************/
static void spi_modifycr1(struct at32_spidev_s *priv,
- uint16_t setbits,
- uint16_t clrbits)
+ uint16_t setbits,
+ uint16_t clrbits)
{
uint16_t cr1;
+
cr1 = spi_getreg(priv, AT32_SPI_CTRL1_OFFSET);
cr1 &= ~clrbits;
cr1 |= setbits;
@@ -942,9 +933,10 @@ static void spi_modifycr1(struct at32_spidev_s *priv,
#if defined(CONFIG_AT32_AT32F43XX) || defined(CONFIG_AT32_SPI_DMA)
static void spi_modifycr2(struct at32_spidev_s *priv, uint16_t setbits,
- uint16_t clrbits)
+ uint16_t clrbits)
{
uint16_t cr2;
+
cr2 = spi_getreg(priv, AT32_SPI_CTRL2_OFFSET);
cr2 &= ~clrbits;
cr2 |= setbits;
@@ -1138,70 +1130,70 @@ static void spi_setmode(struct spi_dev_s *dev, enum
spi_mode_e mode)
/* Yes... Set CR1 appropriately */
switch (mode)
- {
- case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
- setbits = 0;
- clrbits = SPI_CTRL1_CLKPOL | SPI_CTRL1_CLKPHA;
- break;
-
- case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
- setbits = SPI_CTRL1_CLKPHA;
- clrbits = SPI_CTRL1_CLKPOL;
- break;
-
- case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
- setbits = SPI_CTRL1_CLKPOL;
- clrbits = SPI_CTRL1_CLKPHA;
- break;
-
- case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
- setbits = SPI_CTRL1_CLKPOL | SPI_CTRL1_CLKPHA;
- clrbits = 0;
- break;
-
- #ifdef SPI_CTRL2_TIEN /* If MCU supports TI Synchronous Serial Frame
Format */
- case SPIDEV_MODETI:
- setbits = 0;
- clrbits = SPI_CTRL1_CLKPOL | SPI_CTRL1_CLKPHA;
- break;
- #endif
-
- default:
- return;
- }
+ {
+ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+ setbits = 0;
+ clrbits = SPI_CTRL1_CLKPOL | SPI_CTRL1_CLKPHA;
+ break;
+
+ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+ setbits = SPI_CTRL1_CLKPHA;
+ clrbits = SPI_CTRL1_CLKPOL;
+ break;
+
+ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+ setbits = SPI_CTRL1_CLKPOL;
+ clrbits = SPI_CTRL1_CLKPHA;
+ break;
+
+ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+ setbits = SPI_CTRL1_CLKPOL | SPI_CTRL1_CLKPHA;
+ clrbits = 0;
+ break;
+
+#ifdef SPI_CTRL2_TIEN /* If MCU supports TI Synchronous Serial Frame Format
*/
+ case SPIDEV_MODETI:
+ setbits = 0;
+ clrbits = SPI_CTRL1_CLKPOL | SPI_CTRL1_CLKPHA;
+ break;
+#endif
+
+ default:
+ return;
+ }
spi_modifycr1(priv, 0, SPI_CTRL1_SPIEN);
spi_modifycr1(priv, setbits, clrbits);
spi_modifycr1(priv, SPI_CTRL1_SPIEN, 0);
- #ifdef SPI_CTRL2_TIEN /* If MCU supports TI Synchronous Serial Frame
Format */
+#ifdef SPI_CTRL2_TIEN /* If MCU supports TI Synchronous Serial Frame Format
*/
switch (mode)
- {
- case SPIDEV_MODE0:
- case SPIDEV_MODE1:
- case SPIDEV_MODE2:
- case SPIDEV_MODE3:
- setbits = 0;
- clrbits = SPI_CTRL2_TIEN;
- break;
-
- case SPIDEV_MODETI:
- setbits = SPI_CTRL2_TIEN;
- clrbits = 0;
- break;
-
- default:
- return;
- }
+ {
+ case SPIDEV_MODE0:
+ case SPIDEV_MODE1:
+ case SPIDEV_MODE2:
+ case SPIDEV_MODE3:
+ setbits = 0;
+ clrbits = SPI_CTRL2_TIEN;
+ break;
+
+ case SPIDEV_MODETI:
+ setbits = SPI_CTRL2_TIEN;
+ clrbits = 0;
+ break;
+
+ default:
+ return;
+ }
spi_modifycr1(priv, 0, SPI_CTRL1_SPIEN);
spi_modifycr2(priv, setbits, clrbits);
spi_modifycr1(priv, SPI_CTRL1_SPIEN, 0);
- #endif
+#endif
/* Save the mode so that subsequent re-configurations will be
- * faster
- */
+ * faster
+ */
priv->mode = mode;
}
@@ -1237,28 +1229,28 @@ static void spi_setbits(struct spi_dev_s *dev, int
nbits)
/* Yes... Set CR1 appropriately */
switch (nbits)
- {
- case 8:
- setbits = 0;
- clrbits = SPI_CTRL1_FBN;
- break;
-
- case 16:
- setbits = SPI_CTRL1_FBN;
- clrbits = 0;
- break;
-
- default:
- return;
- }
+ {
+ case 8:
+ setbits = 0;
+ clrbits = SPI_CTRL1_FBN;
+ break;
+
+ case 16:
+ setbits = SPI_CTRL1_FBN;
+ clrbits = 0;
+ break;
+
+ default:
+ return;
+ }
spi_modifycr1(priv, 0, SPI_CTRL1_SPIEN);
spi_modifycr1(priv, setbits, clrbits);
spi_modifycr1(priv, SPI_CTRL1_SPIEN, 0);
/* Save the selection so that subsequent re-configurations will be
- * faster.
- */
+ * faster.
+ */
priv->nbits = nbits;
}
@@ -1413,6 +1405,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
#endif
{
struct at32_spidev_s *priv = (struct at32_spidev_s *)dev;
+
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
@@ -1912,7 +1905,7 @@ struct spi_dev_s *at32_spibus_initialize(int bus)
priv->initialized = true;
}
}
- else
+ else
#endif
#ifdef CONFIG_AT32_SPI4
if (bus == 4)
@@ -1937,7 +1930,7 @@ struct spi_dev_s *at32_spibus_initialize(int bus)
priv->initialized = true;
}
}
- else
+ else
#endif
{
spierr("ERROR: Unsupported SPI bus: %d\n", bus);
diff --git a/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c
b/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c
index 04f50729f91..46d09b354d3 100644
--- a/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c
+++ b/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c
@@ -141,9 +141,7 @@
#ifdef CONFIG_STM32_SPI_DMA
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX)
+# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX)
# define SPI_DMA_PRIO DMA_CCR_PRIMED
# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2)
# define SPI_DMA_PRIO DMA_SCR_PRIMED
@@ -151,18 +149,6 @@
# error "Unknown STM32 DMA"
# endif
-# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX)
-# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2)
-# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-# else
-# error "Unknown STM32 DMA"
-# endif
-
#endif
/* DMA channel configuration */
@@ -897,6 +883,7 @@ static void i2s_txdma_sampledone(struct stm32_i2s_s *priv,
int result)
static void i2s_rxdma_timeout(wdparm_t arg)
{
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg;
+
DEBUGASSERT(priv != NULL);
/* Sample DMA registers at the time of the timeout */
@@ -1253,6 +1240,7 @@ static void i2s_rx_schedule(struct stm32_i2s_s *priv, int
result)
static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t result, void *arg)
{
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg;
+
DEBUGASSERT(priv != NULL);
/* Cancel the watchdog timeout */
@@ -1296,6 +1284,7 @@ static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t
result, void *arg)
static void i2s_txdma_timeout(wdparm_t arg)
{
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg;
+
DEBUGASSERT(priv != NULL);
/* Sample DMA registers at the time of the timeout */
@@ -1639,6 +1628,7 @@ static void i2s_tx_schedule(struct stm32_i2s_s *priv, int
result)
static void i2s_txdma_callback(DMA_HANDLE handle, uint8_t result, void *arg)
{
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg;
+
DEBUGASSERT(priv != NULL);
/* Cancel the watchdog timeout */
@@ -1686,17 +1676,17 @@ static int i2s_checkwidth(struct stm32_i2s_s *priv, int
bits)
switch (bits)
{
- case 8:
- priv->align = 0;
- break;
+ case 8:
+ priv->align = 0;
+ break;
- case 16:
- priv->align = 1;
- break;
+ case 16:
+ priv->align = 1;
+ break;
- default:
- i2serr("ERROR: Unsupported or invalid data width: %d\n", bits);
- return (bits < 8 || bits > 16) ? -EINVAL : -ENOSYS;
+ default:
+ i2serr("ERROR: Unsupported or invalid data width: %d\n", bits);
+ return (bits < 8 || bits > 16) ? -EINVAL : -ENOSYS;
}
/* Save the new data width */
@@ -1727,6 +1717,7 @@ static int32_t stm32_i2s_rxsamplerate(struct i2s_dev_s
*dev, uint32_t rate)
{
#if defined(I2S_HAVE_RX) && defined(I2S_HAVE_MCK)
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev;
+
DEBUGASSERT(priv && priv->samplerate >= 0 && rate > 0);
/* Check if the receiver is driven by the MCK */
@@ -2247,22 +2238,22 @@ static int i2s_dma_flags(struct stm32_i2s_s *priv)
{
switch (priv->datalen)
{
- case 8:
+ case 8:
- /* Reconfigure the RX DMA (and TX DMA if applicable) */
+ /* Reconfigure the RX DMA (and TX DMA if applicable) */
- priv->rxccr = SPI_RXDMA8_CONFIG;
- priv->txccr = SPI_TXDMA8_CONFIG;
- break;
+ priv->rxccr = SPI_RXDMA8_CONFIG;
+ priv->txccr = SPI_TXDMA8_CONFIG;
+ break;
- case 16:
- priv->rxccr = SPI_RXDMA16_CONFIG;
- priv->txccr = SPI_TXDMA16_CONFIG;
- break;
+ case 16:
+ priv->rxccr = SPI_RXDMA16_CONFIG;
+ priv->txccr = SPI_TXDMA16_CONFIG;
+ break;
- default:
- i2serr("ERROR: Unsupported data width: %d\n", priv->datalen);
- return -ENOSYS;
+ default:
+ i2serr("ERROR: Unsupported data width: %d\n", priv->datalen);
+ return -ENOSYS;
}
return OK;
diff --git a/arch/arm/src/common/stm32/stm32_spi_m0_v1.c
b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c
index ce9ed4b6508..3a7e85632e2 100644
--- a/arch/arm/src/common/stm32/stm32_spi_m0_v1.c
+++ b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c
@@ -103,17 +103,7 @@
/* SPI DMA priority */
#ifdef CONFIG_STM32_SPI_DMA
-
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# else
-# define SPI_DMA_PRIO DMA_CCR_PRIMED
-# endif
-
-# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-
+# define SPI_DMA_PRIO DMA_CCR_PRIMED
#endif
/* DMA channel configuration */
@@ -642,7 +632,7 @@ static inline uint16_t spi_readword(struct stm32_spidev_s
*priv)
{
return (uint16_t)spi_getreg8(priv, STM32_SPI_DR_OFFSET);
}
- else
+ else
#endif
{
return spi_getreg(priv, STM32_SPI_DR_OFFSET);
@@ -1221,39 +1211,39 @@ static void spi_setmode(struct spi_dev_s *dev, enum
spi_mode_e mode)
switch (mode)
{
- case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
- setbits = 0;
- clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- break;
-
- case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
- setbits = SPI_CR1_CPHA;
- clrbits = SPI_CR1_CPOL;
- break;
-
- case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
- setbits = SPI_CR1_CPOL;
- clrbits = SPI_CR1_CPHA;
- break;
-
- case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
- setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- clrbits = 0;
- break;
-
- default:
- return;
+ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+ setbits = 0;
+ clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+ setbits = SPI_CR1_CPHA;
+ clrbits = SPI_CR1_CPOL;
+ break;
+
+ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+ setbits = SPI_CR1_CPOL;
+ clrbits = SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+ setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ clrbits = 0;
+ break;
+
+ default:
+ return;
}
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits);
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits);
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
- /* Save the mode so that subsequent re-configurations will be
- * faster.
- */
+ /* Save the mode so that subsequent re-configurations will be
+ * faster.
+ */
- priv->mode = mode;
+ priv->mode = mode;
}
}
@@ -1320,18 +1310,18 @@ static void spi_setbits(struct spi_dev_s *dev, int
nbits)
switch (nbits)
{
- case 8:
- setbits = 0;
- clrbits = SPI_CR1_DFF;
- break;
-
- case 16:
- setbits = SPI_CR1_DFF;
- clrbits = 0;
- break;
-
- default:
- return;
+ case 8:
+ setbits = 0;
+ clrbits = SPI_CR1_DFF;
+ break;
+
+ case 16:
+ setbits = SPI_CR1_DFF;
+ clrbits = 0;
+ break;
+
+ default:
+ return;
}
spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
@@ -1505,6 +1495,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
#endif
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
+
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
@@ -1516,8 +1507,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
- uint16_t *dest = (uint16_t *)rxbuffer;
- uint16_t word;
+ uint16_t *dest = (uint16_t *)rxbuffer;
+ uint16_t word;
while (nwords-- > 0)
{
@@ -1551,8 +1542,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
- uint8_t *dest = (uint8_t *)rxbuffer;
- uint8_t word;
+ uint8_t *dest = (uint8_t *)rxbuffer;
+ uint8_t word;
while (nwords-- > 0)
{
@@ -1822,29 +1813,29 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int
domain,
switch (pmstate)
{
- case PM_NORMAL:
- case PM_IDLE:
- break;
+ case PM_NORMAL:
+ case PM_IDLE:
+ break;
- case PM_STANDBY:
- case PM_SLEEP:
+ case PM_STANDBY:
+ case PM_SLEEP:
- if (nxmutex_is_locked(&priv->lock))
- {
- /* Exclusive lock is held, do not allow entry to deeper PM
- * states.
- */
+ if (nxmutex_is_locked(&priv->lock))
+ {
+ /* Exclusive lock is held, do not allow entry to deeper PM
+ * states.
+ */
- return -EBUSY;
- }
+ return -EBUSY;
+ }
- break;
+ break;
- default:
+ default:
- /* Should not get here */
+ /* Should not get here */
- break;
+ break;
}
return OK;
diff --git a/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c
b/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c
index 567f79a95fe..05cdda04224 100644
--- a/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c
+++ b/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c
@@ -98,10 +98,10 @@
#ifdef CONFIG_STM32_SPI_DMA
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX)
|| \
- defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX)
+# if defined(CONFIG_STM32_STM32F10XX) || \
+ defined(CONFIG_STM32_STM32L15XX) || \
+ defined(CONFIG_STM32_STM32F30XX) || \
+ defined(CONFIG_STM32_STM32G4XXX)
# define SPI_DMA_PRIO DMA_CCR_PRIMED
# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2)
# define SPI_DMA_PRIO DMA_SCR_PRIMED
@@ -109,19 +109,6 @@
# error "Unknown STM32 DMA"
# endif
-# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \
- defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX)
-# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2)
-# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-# else
-# error "Unknown STM32 DMA"
-# endif
-
/* DMA channel configuration */
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \
@@ -1228,6 +1215,7 @@ static void spi_modifycr1(struct stm32_spidev_s *priv,
uint16_t clrbits)
{
uint16_t cr1;
+
cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET);
cr1 &= ~clrbits;
cr1 |= setbits;
@@ -1257,7 +1245,8 @@ static void spi_modifycr2(struct stm32_spidev_s *priv,
uint16_t setbits,
uint16_t clrbits)
{
uint16_t cr2;
- cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET);
+
+ cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET);
cr2 &= ~clrbits;
cr2 |= setbits;
spi_putreg(priv, STM32_SPI_CR2_OFFSET, cr2);
@@ -1435,40 +1424,40 @@ static void spi_setmode(struct spi_dev_s *dev, enum
spi_mode_e mode)
switch (mode)
{
- case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
- setbits = 0;
- clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- break;
-
- case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
- setbits = SPI_CR1_CPHA;
- clrbits = SPI_CR1_CPOL;
- break;
-
- case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
- setbits = SPI_CR1_CPOL;
- clrbits = SPI_CR1_CPHA;
- break;
-
- case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
- setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- clrbits = 0;
- break;
+ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+ setbits = 0;
+ clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+ setbits = SPI_CR1_CPHA;
+ clrbits = SPI_CR1_CPOL;
+ break;
+
+ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+ setbits = SPI_CR1_CPOL;
+ clrbits = SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+ setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ clrbits = 0;
+ break;
#ifdef SPI_CR2_FRF /* If MCU supports TI Synchronous Serial Frame Format */
- case SPIDEV_MODETI:
- setbits = 0;
- clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- break;
+ case SPIDEV_MODETI:
+ setbits = 0;
+ clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ break;
#endif
- default:
- return;
+ default:
+ return;
}
- spi_modifycr1(priv, 0, SPI_CR1_SPE);
- spi_modifycr1(priv, setbits, clrbits);
- spi_modifycr1(priv, SPI_CR1_SPE, 0);
+ spi_modifycr1(priv, 0, SPI_CR1_SPE);
+ spi_modifycr1(priv, setbits, clrbits);
+ spi_modifycr1(priv, SPI_CR1_SPE, 0);
#ifdef SPI_CR2_FRF /* If MCU supports TI Synchronous Serial Frame Format */
switch (mode)
@@ -1495,11 +1484,11 @@ static void spi_setmode(struct spi_dev_s *dev, enum
spi_mode_e mode)
spi_modifycr1(priv, SPI_CR1_SPE, 0);
#endif
- /* Save the mode so that subsequent re-configurations will be
- * faster
- */
+ /* Save the mode so that subsequent re-configurations will be
+ * faster
+ */
- priv->mode = mode;
+ priv->mode = mode;
}
}
@@ -1566,18 +1555,18 @@ static void spi_setbits(struct spi_dev_s *dev, int
nbits)
switch (nbits)
{
- case 8:
- setbits = 0;
- clrbits = SPI_CR1_DFF;
- break;
+ case 8:
+ setbits = 0;
+ clrbits = SPI_CR1_DFF;
+ break;
- case 16:
- setbits = SPI_CR1_DFF;
- clrbits = 0;
- break;
+ case 16:
+ setbits = SPI_CR1_DFF;
+ clrbits = 0;
+ break;
- default:
- return;
+ default:
+ return;
}
spi_modifycr1(priv, 0, SPI_CR1_SPE);
@@ -1736,6 +1725,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
#endif
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
+
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
@@ -1747,8 +1737,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
- uint16_t *dest = (uint16_t *)rxbuffer;
- uint16_t word;
+ uint16_t *dest = (uint16_t *)rxbuffer;
+ uint16_t word;
while (nwords-- > 0)
{
@@ -1780,8 +1770,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
- uint8_t *dest = (uint8_t *)rxbuffer;
- uint8_t word;
+ uint8_t *dest = (uint8_t *)rxbuffer;
+ uint8_t word;
while (nwords-- > 0)
{
diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c
index e00f9d7b03c..7764ffd60ea 100644
--- a/arch/arm/src/stm32f7/stm32_i2s.c
+++ b/arch/arm/src/stm32f7/stm32_i2s.c
@@ -177,18 +177,12 @@
#ifdef CONFIG_STM32_SPI_DMA
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# elif defined(DMA_SCR_PRIMED)
+# if defined(DMA_SCR_PRIMED)
# define SPI_DMA_PRIO DMA_SCR_PRILO
# else
# error "Unknown STM32 DMA"
# endif
-# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-
/* DMA channel configuration */
# define SPI_RXDMA16_CONFIG
(SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M)
@@ -944,6 +938,7 @@ static void i2s_txdma_sampledone(struct stm32_i2s_s *priv,
int result)
static void i2s_rxdma_timeout(wdparm_t arg)
{
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg;
+
DEBUGASSERT(priv != NULL);
/* Sample DMA registers at the time of the timeout */
@@ -1300,6 +1295,7 @@ static void i2s_rx_schedule(struct stm32_i2s_s *priv, int
result)
static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t result, void *arg)
{
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg;
+
DEBUGASSERT(priv != NULL);
/* Cancel the watchdog timeout */
@@ -1343,6 +1339,7 @@ static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t
result, void *arg)
static void i2s_txdma_timeout(wdparm_t arg)
{
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg;
+
DEBUGASSERT(priv != NULL);
/* Sample DMA registers at the time of the timeout */
@@ -1686,6 +1683,7 @@ static void i2s_tx_schedule(struct stm32_i2s_s *priv, int
result)
static void i2s_txdma_callback(DMA_HANDLE handle, uint8_t result, void *arg)
{
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg;
+
DEBUGASSERT(priv != NULL);
/* Cancel the watchdog timeout */
@@ -1733,17 +1731,17 @@ static int i2s_checkwidth(struct stm32_i2s_s *priv, int
bits)
switch (bits)
{
- case 8:
- priv->align = 0;
- break;
+ case 8:
+ priv->align = 0;
+ break;
- case 16:
- priv->align = 1;
- break;
+ case 16:
+ priv->align = 1;
+ break;
- default:
- i2serr("ERROR: Unsupported or invalid data width: %d\n", bits);
- return (bits < 8 || bits > 16) ? -EINVAL : -ENOSYS;
+ default:
+ i2serr("ERROR: Unsupported or invalid data width: %d\n", bits);
+ return (bits < 8 || bits > 16) ? -EINVAL : -ENOSYS;
}
/* Save the new data width */
@@ -1774,6 +1772,7 @@ static int32_t stm32_i2s_rxsamplerate(struct i2s_dev_s
*dev, uint32_t rate)
{
#if defined(I2S_HAVE_RX) && defined(I2S_HAVE_MCK)
struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev;
+
DEBUGASSERT(priv && priv->samplerate >= 0 && rate > 0);
/* Check if the receiver is driven by the MCK */
@@ -2300,22 +2299,22 @@ static int i2s_dma_flags(struct stm32_i2s_s *priv)
{
switch (priv->datalen)
{
- case 8:
+ case 8:
- /* Reconfigure the RX DMA (and TX DMA if applicable) */
+ /* Reconfigure the RX DMA (and TX DMA if applicable) */
- priv->rxccr = SPI_RXDMA8_CONFIG;
- priv->txccr = SPI_TXDMA8_CONFIG;
- break;
+ priv->rxccr = SPI_RXDMA8_CONFIG;
+ priv->txccr = SPI_TXDMA8_CONFIG;
+ break;
- case 16:
- priv->rxccr = SPI_RXDMA16_CONFIG;
- priv->txccr = SPI_TXDMA16_CONFIG;
- break;
+ case 16:
+ priv->rxccr = SPI_RXDMA16_CONFIG;
+ priv->txccr = SPI_TXDMA16_CONFIG;
+ break;
- default:
- i2serr("ERROR: Unsupported data width: %d\n", priv->datalen);
- return -ENOSYS;
+ default:
+ i2serr("ERROR: Unsupported data width: %d\n", priv->datalen);
+ return -ENOSYS;
}
return OK;
diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c
index 2b43927a3ec..c96f5b5c1c2 100644
--- a/arch/arm/src/stm32f7/stm32_spi.c
+++ b/arch/arm/src/stm32f7/stm32_spi.c
@@ -99,18 +99,12 @@
#ifdef CONFIG_STM32_SPI_DMA
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# elif defined(DMA_SCR_PRIMED)
+# if defined(DMA_SCR_PRIMED)
# define SPI_DMA_PRIO DMA_SCR_PRILO
# else
# error "Unknown STM32 DMA"
# endif
-# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-
/* DMA channel configuration */
# define SPI_RXDMA16_CONFIG
(SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M)
@@ -1198,6 +1192,7 @@ static void spi_modifycr1(struct stm32_spidev_s *priv,
uint16_t setbits,
uint16_t clrbits)
{
uint16_t cr1;
+
cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET);
cr1 &= ~clrbits;
cr1 |= setbits;
@@ -1224,6 +1219,7 @@ static void spi_modifycr2(struct stm32_spidev_s *priv,
uint16_t setbits,
uint16_t clrbits)
{
uint16_t cr2;
+
cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET);
cr2 &= ~clrbits;
cr2 |= setbits;
@@ -1411,28 +1407,28 @@ static void spi_setmode(struct spi_dev_s *dev, enum
spi_mode_e mode)
switch (mode)
{
- case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
- setbits = 0;
- clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- break;
-
- case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
- setbits = SPI_CR1_CPHA;
- clrbits = SPI_CR1_CPOL;
- break;
-
- case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
- setbits = SPI_CR1_CPOL;
- clrbits = SPI_CR1_CPHA;
- break;
-
- case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
- setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- clrbits = 0;
- break;
-
- default:
- return;
+ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+ setbits = 0;
+ clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+ setbits = SPI_CR1_CPHA;
+ clrbits = SPI_CR1_CPOL;
+ break;
+
+ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+ setbits = SPI_CR1_CPOL;
+ clrbits = SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+ setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ clrbits = 0;
+ break;
+
+ default:
+ return;
}
/* Disable SPI then change mode */
@@ -1703,6 +1699,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
#endif
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
+
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
@@ -1714,8 +1711,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
- uint16_t *dest = (uint16_t *)rxbuffer;
- uint16_t word;
+ uint16_t *dest = (uint16_t *)rxbuffer;
+ uint16_t word;
while (nwords-- > 0)
{
@@ -1747,8 +1744,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
- uint8_t *dest = (uint8_t *)rxbuffer;
- uint8_t word;
+ uint8_t *dest = (uint8_t *)rxbuffer;
+ uint8_t word;
while (nwords-- > 0)
{
@@ -2086,31 +2083,31 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int
domain,
switch (pmstate)
{
- case PM_NORMAL:
- case PM_IDLE:
- break;
+ case PM_NORMAL:
+ case PM_IDLE:
+ break;
- case PM_STANDBY:
- case PM_SLEEP:
+ case PM_STANDBY:
+ case PM_SLEEP:
- /* Check if exclusive lock for SPI bus is held. */
+ /* Check if exclusive lock for SPI bus is held. */
- if (nxmutex_is_locked(&priv->lock))
- {
- /* Exclusive lock is held, do not allow entry to deeper
- * PM states.
- */
+ if (nxmutex_is_locked(&priv->lock))
+ {
+ /* Exclusive lock is held, do not allow entry to deeper
+ * PM states.
+ */
- return -EBUSY;
- }
+ return -EBUSY;
+ }
- break;
+ break;
- default:
+ default:
- /* Should not get here */
+ /* Should not get here */
- break;
+ break;
}
return OK;
diff --git a/arch/arm/src/stm32h5/stm32_spi.c b/arch/arm/src/stm32h5/stm32_spi.c
index 312a4484043..25e23d3b078 100644
--- a/arch/arm/src/stm32h5/stm32_spi.c
+++ b/arch/arm/src/stm32h5/stm32_spi.c
@@ -105,21 +105,15 @@
#endif
/* SPI DMA priority */
+
#ifdef CONFIG_STM32_SPI_DMA
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# elif defined(GPDMACFG_PRIO_LM)
+# if defined(GPDMACFG_PRIO_LM)
# define SPI_DMA_PRIO GPDMACFG_PRIO_LL
# else
# error "Unknown STM32 DMA"
# endif
-# if SPI_DMA_PRIO != GPDMACFG_PRIO_LL && SPI_DMA_PRIO != GPDMACFG_PRIO_LM \
- && SPI_DMA_PRIO != GPMDACFG_PRIO_LH && SPI_DMA_PRIO != GPDMACFG_PRIO_H
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-
/* DMA channel configuration.
* For RX, memory is the destination (DDW)
* and peripheral is the source (SDW).
@@ -1777,28 +1771,28 @@ static void spi_setmode(struct spi_dev_s *dev, enum
spi_mode_e mode)
switch (mode)
{
- case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
- setbits = 0;
- clrbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
- break;
-
- case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
- setbits = SPI_CFG2_CPHA;
- clrbits = SPI_CFG2_CPOL;
- break;
-
- case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
- setbits = SPI_CFG2_CPOL;
- clrbits = SPI_CFG2_CPHA;
- break;
-
- case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
- setbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
- clrbits = 0;
- break;
-
- default:
- return;
+ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+ setbits = 0;
+ clrbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
+ break;
+
+ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+ setbits = SPI_CFG2_CPHA;
+ clrbits = SPI_CFG2_CPOL;
+ break;
+
+ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+ setbits = SPI_CFG2_CPOL;
+ clrbits = SPI_CFG2_CPHA;
+ break;
+
+ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+ setbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
+ clrbits = 0;
+ break;
+
+ default:
+ return;
}
spi_enable(priv, false);
@@ -2054,6 +2048,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
size_t nwords)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
+
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
@@ -2080,11 +2075,12 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
{
/* 16-bit mode */
- const uint16_t *src = (const uint16_t *)txbuffer;
- uint16_t *dest = (uint16_t *)rxbuffer;
- uint16_t word;
- size_t n_tx_words = 0;
- size_t n_rx_words = 0;
+ const uint16_t *src = (const uint16_t *)txbuffer;
+ uint16_t *dest = (uint16_t *)rxbuffer;
+ uint16_t word;
+ size_t n_tx_words = 0;
+ size_t n_rx_words = 0;
+
while (n_tx_words < nwords)
{
/* Get the next word to write. Is there a source buffer? */
@@ -2439,7 +2435,7 @@ static void spi_exchange_dma(struct spi_dev_s *dev, const
void *txbuffer,
}
#ifdef CONFIG_SPI_TRIGGER
- priv->trigarmed = false;
+ priv->trigarmed = false;
#endif
}
#endif /* CONFIG_STM32_SPI_DMA */
@@ -2609,31 +2605,31 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int
domain,
switch (pmstate)
{
- case PM_NORMAL:
- case PM_IDLE:
- break;
+ case PM_NORMAL:
+ case PM_IDLE:
+ break;
- case PM_STANDBY:
- case PM_SLEEP:
+ case PM_STANDBY:
+ case PM_SLEEP:
- /* Check if exclusive lock for SPI bus is held. */
+ /* Check if exclusive lock for SPI bus is held. */
- if (nxmutex_is_locked(&priv->lock))
- {
- /* Exclusive lock is held, do not allow entry to deeper PM
- * states.
- */
+ if (nxmutex_is_locked(&priv->lock))
+ {
+ /* Exclusive lock is held, do not allow entry to deeper PM
+ * states.
+ */
- return -EBUSY;
- }
+ return -EBUSY;
+ }
- break;
+ break;
- default:
+ default:
- /* Should not get here */
+ /* Should not get here */
- break;
+ break;
}
return OK;
@@ -2694,19 +2690,22 @@ static void spi_bus_initialize(struct stm32_spidev_s
*priv)
switch (priv->config)
{
- default:
- case FULL_DUPLEX:
- setbits |= SPI_CFG2_COMM_FULL;
- break;
- case SIMPLEX_TX:
- setbits |= SPI_CFG2_COMM_STX;
- break;
- case SIMPLEX_RX:
- setbits |= SPI_CFG2_COMM_SRX;
- break;
- case HALF_DUPLEX:
- setbits |= SPI_CFG2_COMM_HALF;
- break;
+ default:
+ case FULL_DUPLEX:
+ setbits |= SPI_CFG2_COMM_FULL;
+ break;
+
+ case SIMPLEX_TX:
+ setbits |= SPI_CFG2_COMM_STX;
+ break;
+
+ case SIMPLEX_RX:
+ setbits |= SPI_CFG2_COMM_SRX;
+ break;
+
+ case HALF_DUPLEX:
+ setbits |= SPI_CFG2_COMM_HALF;
+ break;
}
spi_modifyreg(priv, STM32_SPI_CFG2_OFFSET, clrbits, setbits);
diff --git a/arch/arm/src/stm32h7/stm32_spi.c b/arch/arm/src/stm32h7/stm32_spi.c
index 7ca1e810308..d01b059b550 100644
--- a/arch/arm/src/stm32h7/stm32_spi.c
+++ b/arch/arm/src/stm32h7/stm32_spi.c
@@ -101,18 +101,12 @@
#ifdef CONFIG_STM32_SPI_DMA
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# elif defined(DMA_SCR_PRIMED)
+# if defined(DMA_SCR_PRIMED)
# define SPI_DMA_PRIO DMA_SCR_PRILO
# else
# error "Unknown STM32 DMA"
# endif
-# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-
/* DMA channel configuration */
# define SPI_RXDMA16_CONFIG
(SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M)
@@ -1660,28 +1654,28 @@ static void spi_setmode(struct spi_dev_s *dev, enum
spi_mode_e mode)
switch (mode)
{
- case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
- setbits = 0;
- clrbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
- break;
-
- case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
- setbits = SPI_CFG2_CPHA;
- clrbits = SPI_CFG2_CPOL;
- break;
-
- case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
- setbits = SPI_CFG2_CPOL;
- clrbits = SPI_CFG2_CPHA;
- break;
-
- case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
- setbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
- clrbits = 0;
- break;
-
- default:
- return;
+ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+ setbits = 0;
+ clrbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
+ break;
+
+ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+ setbits = SPI_CFG2_CPHA;
+ clrbits = SPI_CFG2_CPOL;
+ break;
+
+ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+ setbits = SPI_CFG2_CPOL;
+ clrbits = SPI_CFG2_CPHA;
+ break;
+
+ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+ setbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
+ clrbits = 0;
+ break;
+
+ default:
+ return;
}
spi_enable(priv, false);
@@ -1941,6 +1935,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
#endif
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
+
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
@@ -1957,8 +1952,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
- uint16_t *dest = (uint16_t *)rxbuffer;
- uint16_t word;
+ uint16_t *dest = (uint16_t *)rxbuffer;
+ uint16_t word;
while (nwords-- > 0)
{
@@ -1990,8 +1985,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
- uint8_t *dest = (uint8_t *)rxbuffer;
- uint8_t word;
+ uint8_t *dest = (uint8_t *)rxbuffer;
+ uint8_t word;
while (nwords-- > 0)
{
@@ -2261,7 +2256,7 @@ static void spi_exchange(struct spi_dev_s *dev, const
void *txbuffer,
}
#ifdef CONFIG_SPI_TRIGGER
- priv->trigarmed = false;
+ priv->trigarmed = false;
#endif
}
#endif /* CONFIG_STM32_SPI_DMA */
@@ -2405,31 +2400,31 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int
domain,
switch (pmstate)
{
- case PM_NORMAL:
- case PM_IDLE:
- break;
+ case PM_NORMAL:
+ case PM_IDLE:
+ break;
- case PM_STANDBY:
- case PM_SLEEP:
+ case PM_STANDBY:
+ case PM_SLEEP:
- /* Check if exclusive lock for SPI bus is held. */
+ /* Check if exclusive lock for SPI bus is held. */
- if (nxmutex_is_locked(&priv->lock))
- {
- /* Exclusive lock is held, do not allow entry to deeper PM
- * states.
- */
+ if (nxmutex_is_locked(&priv->lock))
+ {
+ /* Exclusive lock is held, do not allow entry to deeper PM
+ * states.
+ */
- return -EBUSY;
- }
+ return -EBUSY;
+ }
- break;
+ break;
- default:
+ default:
- /* Should not get here */
+ /* Should not get here */
- break;
+ break;
}
return OK;
@@ -2490,19 +2485,22 @@ static void spi_bus_initialize(struct stm32_spidev_s
*priv)
switch (priv->config)
{
- default:
- case FULL_DUPLEX:
- setbits |= SPI_CFG2_COMM_FULL;
- break;
- case SIMPLEX_TX:
- setbits |= SPI_CFG2_COMM_STX;
- break;
- case SIMPLEX_RX:
- setbits |= SPI_CFG2_COMM_SRX;
- break;
- case HALF_DUPLEX:
- setbits |= SPI_CFG2_COMM_HALF;
- break;
+ default:
+ case FULL_DUPLEX:
+ setbits |= SPI_CFG2_COMM_FULL;
+ break;
+
+ case SIMPLEX_TX:
+ setbits |= SPI_CFG2_COMM_STX;
+ break;
+
+ case SIMPLEX_RX:
+ setbits |= SPI_CFG2_COMM_SRX;
+ break;
+
+ case HALF_DUPLEX:
+ setbits |= SPI_CFG2_COMM_HALF;
+ break;
}
spi_modifyreg(priv, STM32_SPI_CFG2_OFFSET, clrbits, setbits);
diff --git a/arch/arm/src/stm32h7/stm32_spi_slave.c
b/arch/arm/src/stm32h7/stm32_spi_slave.c
index 83499c4d8ef..17cec504390 100644
--- a/arch/arm/src/stm32h7/stm32_spi_slave.c
+++ b/arch/arm/src/stm32h7/stm32_spi_slave.c
@@ -81,18 +81,12 @@
#ifdef CONFIG_STM32_SPI_DMA
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# elif defined(DMA_SCR_PRIMED)
+# if defined(DMA_SCR_PRIMED)
# define SPI_DMA_PRIO DMA_SCR_PRILO
# else
# error "Unknown STM32 DMA"
# endif
-# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-
/* DMA channel configuration */
# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO | DMA_SCR_MSIZE_16BITS | \
@@ -986,28 +980,28 @@ static void spi_setmode(struct spi_slave_ctrlr_s *ctrlr,
switch (mode)
{
- case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
- setbits = 0;
- clrbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
- break;
-
- case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
- setbits = SPI_CFG2_CPHA;
- clrbits = SPI_CFG2_CPOL;
- break;
-
- case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
- setbits = SPI_CFG2_CPOL;
- clrbits = SPI_CFG2_CPHA;
- break;
-
- case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
- setbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
- clrbits = 0;
- break;
-
- default:
- return;
+ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+ setbits = 0;
+ clrbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
+ break;
+
+ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+ setbits = SPI_CFG2_CPHA;
+ clrbits = SPI_CFG2_CPOL;
+ break;
+
+ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+ setbits = SPI_CFG2_CPOL;
+ clrbits = SPI_CFG2_CPHA;
+ break;
+
+ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+ setbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
+ clrbits = 0;
+ break;
+
+ default:
+ return;
}
/* Change SPI mode */
@@ -1554,29 +1548,31 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int
domain,
switch (pmstate)
{
- case PM_NORMAL:
- case PM_IDLE:
- break;
+ case PM_NORMAL:
+ case PM_IDLE:
+ break;
- case PM_STANDBY:
- case PM_SLEEP:
+ case PM_STANDBY:
+ case PM_SLEEP:
- /* Check if exclusive lock for SPI bus is held. */
+ /* Check if exclusive lock for SPI bus is held. */
- /* If exclusive lock is held, do not allow entry to deeper PM states */
+ /* If exclusive lock is held, do not allow entry to deeper PM
+ * states.
+ */
- if (nxmutex_is_locked(&priv->lock))
- {
- return -EBUSY;
- }
+ if (nxmutex_is_locked(&priv->lock))
+ {
+ return -EBUSY;
+ }
- break;
+ break;
- default:
+ default:
- /* Should not get here */
+ /* Should not get here */
- break;
+ break;
}
return OK;
@@ -1633,19 +1629,22 @@ static void spi_slave_initialize(struct stm32_spidev_s
*priv)
switch (priv->config)
{
- default:
- case FULL_DUPLEX:
- setbits |= SPI_CFG2_COMM_FULL;
- break;
- case SIMPLEX_TX:
- setbits |= SPI_CFG2_COMM_STX;
- break;
- case SIMPLEX_RX:
- setbits |= SPI_CFG2_COMM_SRX;
- break;
- case HALF_DUPLEX:
- setbits |= SPI_CFG2_COMM_HALF;
- break;
+ default:
+ case FULL_DUPLEX:
+ setbits |= SPI_CFG2_COMM_FULL;
+ break;
+
+ case SIMPLEX_TX:
+ setbits |= SPI_CFG2_COMM_STX;
+ break;
+
+ case SIMPLEX_RX:
+ setbits |= SPI_CFG2_COMM_SRX;
+ break;
+
+ case HALF_DUPLEX:
+ setbits |= SPI_CFG2_COMM_HALF;
+ break;
}
spi_modifyreg(priv, STM32_SPI_CFG2_OFFSET, clrbits, setbits);
diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c
b/arch/arm/src/stm32l4/stm32l4_spi.c
index 8eb04f9ef9e..1462a902764 100644
--- a/arch/arm/src/stm32l4/stm32l4_spi.c
+++ b/arch/arm/src/stm32l4/stm32l4_spi.c
@@ -104,17 +104,7 @@
/* SPI DMA priority */
#ifdef CONFIG_STM32_SPI_DMA
-
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# else
-# define SPI_DMA_PRIO DMA_CCR_PRIMED
-# endif
-
-# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-
+# define SPI_DMA_PRIO DMA_CCR_PRIMED
#endif
/* DMA channel configuration */
@@ -1103,39 +1093,39 @@ static void spi_setmode(struct spi_dev_s *dev, enum
spi_mode_e mode)
switch (mode)
{
- case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
- setbits = 0;
- clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- break;
-
- case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
- setbits = SPI_CR1_CPHA;
- clrbits = SPI_CR1_CPOL;
- break;
-
- case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
- setbits = SPI_CR1_CPOL;
- clrbits = SPI_CR1_CPHA;
- break;
-
- case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
- setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- clrbits = 0;
- break;
-
- default:
- return;
+ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+ setbits = 0;
+ clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+ setbits = SPI_CR1_CPHA;
+ clrbits = SPI_CR1_CPOL;
+ break;
+
+ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+ setbits = SPI_CR1_CPOL;
+ clrbits = SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+ setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ clrbits = 0;
+ break;
+
+ default:
+ return;
}
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits);
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits);
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
- /* Save the mode so that subsequent re-configurations will be
- * faster.
- */
+ /* Save the mode so that subsequent re-configurations will be
+ * faster.
+ */
- priv->mode = mode;
+ priv->mode = mode;
}
}
@@ -1365,6 +1355,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
#endif
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
+
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
@@ -1376,8 +1367,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
- uint16_t *dest = (uint16_t *)rxbuffer;
- uint16_t word;
+ uint16_t *dest = (uint16_t *)rxbuffer;
+ uint16_t word;
while (nwords-- > 0)
{
@@ -1409,8 +1400,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
- uint8_t *dest = (uint8_t *)rxbuffer;
- uint8_t word;
+ uint8_t *dest = (uint8_t *)rxbuffer;
+ uint8_t word;
while (nwords-- > 0)
{
@@ -1669,31 +1660,31 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int
domain,
switch (pmstate)
{
- case PM_NORMAL:
- case PM_IDLE:
- break;
+ case PM_NORMAL:
+ case PM_IDLE:
+ break;
- case PM_STANDBY:
- case PM_SLEEP:
+ case PM_STANDBY:
+ case PM_SLEEP:
- /* Check if exclusive lock for SPI bus is held. */
+ /* Check if exclusive lock for SPI bus is held. */
- if (nxmutex_is_locked(&priv->lock))
- {
- /* Exclusive lock is held, do not allow entry to deeper PM
- * states.
- */
+ if (nxmutex_is_locked(&priv->lock))
+ {
+ /* Exclusive lock is held, do not allow entry to deeper PM
+ * states.
+ */
- return -EBUSY;
- }
+ return -EBUSY;
+ }
- break;
+ break;
- default:
+ default:
- /* Should not get here */
+ /* Should not get here */
- break;
+ break;
}
return OK;
diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c
b/arch/arm/src/stm32l5/stm32l5_spi.c
index 88f25011ead..bb2c5d9f8c3 100644
--- a/arch/arm/src/stm32l5/stm32l5_spi.c
+++ b/arch/arm/src/stm32l5/stm32l5_spi.c
@@ -107,17 +107,7 @@
/* SPI DMA priority */
#ifdef CONFIG_STM32_SPI_DMA
-
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# else
-# define SPI_DMA_PRIO DMA_CCR_PRIMED
-# endif
-
-# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-
+# define SPI_DMA_PRIO DMA_CCR_PRIMED
#endif
/* DMA channel configuration */
diff --git a/arch/arm/src/stm32u5/stm32_spi.c b/arch/arm/src/stm32u5/stm32_spi.c
index 82ceb35c60d..458287a1b57 100644
--- a/arch/arm/src/stm32u5/stm32_spi.c
+++ b/arch/arm/src/stm32u5/stm32_spi.c
@@ -99,18 +99,12 @@
#ifdef CONFIG_STM32_SPI_DMA
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# elif defined(DMA_SCR_PRIMED)
+# if defined(DMA_SCR_PRIMED)
# define SPI_DMA_PRIO DMA_SCR_PRILO
# else
# error "Unknown STM32 DMA"
# endif
-# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-
/* DMA channel configuration */
# define SPI_RXDMA16_CONFIG
(SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M)
@@ -1393,28 +1387,28 @@ static void spi_setmode(struct spi_dev_s *dev, enum
spi_mode_e mode)
switch (mode)
{
- case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
- setbits = 0;
- clrbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
- break;
-
- case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
- setbits = SPI_CFG2_CPHA;
- clrbits = SPI_CFG2_CPOL;
- break;
-
- case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
- setbits = SPI_CFG2_CPOL;
- clrbits = SPI_CFG2_CPHA;
- break;
-
- case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
- setbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
- clrbits = 0;
- break;
-
- default:
- return;
+ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+ setbits = 0;
+ clrbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
+ break;
+
+ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+ setbits = SPI_CFG2_CPHA;
+ clrbits = SPI_CFG2_CPOL;
+ break;
+
+ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+ setbits = SPI_CFG2_CPOL;
+ clrbits = SPI_CFG2_CPHA;
+ break;
+
+ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+ setbits = SPI_CFG2_CPOL | SPI_CFG2_CPHA;
+ clrbits = 0;
+ break;
+
+ default:
+ return;
}
spi_enable(priv, false);
@@ -1674,6 +1668,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
#endif
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
+
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
@@ -1690,8 +1685,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
- uint16_t *dest = (uint16_t *)rxbuffer;
- uint16_t word;
+ uint16_t *dest = (uint16_t *)rxbuffer;
+ uint16_t word;
while (nwords-- > 0)
{
@@ -1723,8 +1718,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
- uint8_t *dest = (uint8_t *)rxbuffer;
- uint8_t word;
+ uint8_t *dest = (uint8_t *)rxbuffer;
+ uint8_t word;
while (nwords-- > 0)
{
@@ -1992,7 +1987,7 @@ static void spi_exchange(struct spi_dev_s *dev, const
void *txbuffer,
}
#ifdef CONFIG_SPI_TRIGGER
- priv->trigarmed = false;
+ priv->trigarmed = false;
#endif
}
#endif /* CONFIG_STM32_SPI_DMA */
@@ -2136,31 +2131,31 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int
domain,
switch (pmstate)
{
- case PM_NORMAL:
- case PM_IDLE:
- break;
+ case PM_NORMAL:
+ case PM_IDLE:
+ break;
- case PM_STANDBY:
- case PM_SLEEP:
+ case PM_STANDBY:
+ case PM_SLEEP:
- /* Check if exclusive lock for SPI bus is held. */
+ /* Check if exclusive lock for SPI bus is held. */
- if (nxmutex_is_locked(&priv->lock))
- {
- /* Exclusive lock is held, do not allow entry to deeper PM
- * states.
- */
+ if (nxmutex_is_locked(&priv->lock))
+ {
+ /* Exclusive lock is held, do not allow entry to deeper PM
+ * states.
+ */
- return -EBUSY;
- }
+ return -EBUSY;
+ }
- break;
+ break;
- default:
+ default:
- /* Should not get here */
+ /* Should not get here */
- break;
+ break;
}
return OK;
@@ -2221,19 +2216,22 @@ static void spi_bus_initialize(struct stm32_spidev_s
*priv)
switch (priv->config)
{
- default:
- case FULL_DUPLEX:
- setbits |= SPI_CFG2_COMM_FULL;
- break;
- case SIMPLEX_TX:
- setbits |= SPI_CFG2_COMM_STX;
- break;
- case SIMPLEX_RX:
- setbits |= SPI_CFG2_COMM_SRX;
- break;
- case HALF_DUPLEX:
- setbits |= SPI_CFG2_COMM_HALF;
- break;
+ default:
+ case FULL_DUPLEX:
+ setbits |= SPI_CFG2_COMM_FULL;
+ break;
+
+ case SIMPLEX_TX:
+ setbits |= SPI_CFG2_COMM_STX;
+ break;
+
+ case SIMPLEX_RX:
+ setbits |= SPI_CFG2_COMM_SRX;
+ break;
+
+ case HALF_DUPLEX:
+ setbits |= SPI_CFG2_COMM_HALF;
+ break;
}
spi_modifyreg(priv, STM32_SPI_CFG2_OFFSET, clrbits, setbits);
diff --git a/arch/arm/src/stm32wb/stm32wb_spi.c
b/arch/arm/src/stm32wb/stm32wb_spi.c
index 515f98920ab..2531deae35c 100644
--- a/arch/arm/src/stm32wb/stm32wb_spi.c
+++ b/arch/arm/src/stm32wb/stm32wb_spi.c
@@ -103,17 +103,7 @@
/* SPI DMA priority */
#ifdef CONFIG_STM32_SPI_DMA
-
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# else
-# define SPI_DMA_PRIO DMA_CCR_PRIMED
-# endif
-
-# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-
+# define SPI_DMA_PRIO DMA_CCR_PRIMED
#endif
/* DMA channel configuration */
@@ -1064,15 +1054,15 @@ static void spi_setmode(struct spi_dev_s *dev, enum
spi_mode_e mode)
return;
}
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits);
- spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits);
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
- /* Save the mode so that subsequent re-configurations will be
- * faster.
- */
+ /* Save the mode so that subsequent re-configurations will be
+ * faster.
+ */
- priv->mode = mode;
+ priv->mode = mode;
}
}
@@ -1301,6 +1291,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
#endif
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
+
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.c
b/arch/arm/src/stm32wl5/stm32wl5_spi.c
index 9c7f0008af6..3d688369913 100644
--- a/arch/arm/src/stm32wl5/stm32wl5_spi.c
+++ b/arch/arm/src/stm32wl5/stm32wl5_spi.c
@@ -101,23 +101,13 @@
#ifdef CONFIG_STM32_SPI_DMA
-# if defined(CONFIG_SPI_DMAPRIO)
-# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
-# elif defined(CONFIG_STM32_STM32WL5XXX_CPU1
-#warning "Verify, read doc and Implement"
+# if defined(CONFIG_STM32_STM32WL5XXX_CPU1)
+# warning "Verify, read doc and Implement"
# define SPI_DMA_PRIO DMA_CCR_PRIMED
# else
# error "Unknown STM32WL5 DMA"
# endif
-# if defined(CONFIG_STM32_STM32WL5XXX_CPU1)
-# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
-# error "Illegal value for CONFIG_SPI_DMAPRIO"
-# endif
-# else
-# error "Unknown STM32 DMA"
-# endif
-
/* DMA channel configuration */
#if defined(CONFIG_STM32_STM32WL5XXX_CPU1)
@@ -875,6 +865,7 @@ static void spi_modifycr1(struct stm32_spidev_s *priv,
uint16_t clrbits)
{
uint16_t cr1;
+
cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET);
cr1 &= ~clrbits;
cr1 |= setbits;
@@ -904,6 +895,7 @@ static void spi_modifycr2(struct stm32_spidev_s *priv,
uint16_t setbits,
uint16_t clrbits)
{
uint16_t cr2;
+
cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET);
cr2 &= ~clrbits;
cr2 |= setbits;
@@ -1083,40 +1075,40 @@ static void spi_setmode(struct spi_dev_s *dev, enum
spi_mode_e mode)
switch (mode)
{
- case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
- setbits = 0;
- clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- break;
-
- case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
- setbits = SPI_CR1_CPHA;
- clrbits = SPI_CR1_CPOL;
- break;
-
- case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
- setbits = SPI_CR1_CPOL;
- clrbits = SPI_CR1_CPHA;
- break;
-
- case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
- setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- clrbits = 0;
- break;
+ case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
+ setbits = 0;
+ clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
+ setbits = SPI_CR1_CPHA;
+ clrbits = SPI_CR1_CPOL;
+ break;
+
+ case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
+ setbits = SPI_CR1_CPOL;
+ clrbits = SPI_CR1_CPHA;
+ break;
+
+ case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
+ setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ clrbits = 0;
+ break;
#ifdef SPI_CR2_FRF /* If MCU supports TI Synchronous Serial Frame Format */
- case SPIDEV_MODETI:
- setbits = 0;
- clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
- break;
+ case SPIDEV_MODETI:
+ setbits = 0;
+ clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
+ break;
#endif
- default:
- return;
+ default:
+ return;
}
- spi_modifycr1(priv, 0, SPI_CR1_SPE);
- spi_modifycr1(priv, setbits, clrbits);
- spi_modifycr1(priv, SPI_CR1_SPE, 0);
+ spi_modifycr1(priv, 0, SPI_CR1_SPE);
+ spi_modifycr1(priv, setbits, clrbits);
+ spi_modifycr1(priv, SPI_CR1_SPE, 0);
#ifdef SPI_CR2_FRF /* If MCU supports TI Synchronous Serial Frame Format */
switch (mode)
@@ -1360,6 +1352,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
#endif
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
+
DEBUGASSERT(priv && priv->spibase);
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
