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xiaoxiang781216 pushed a commit to branch master
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The following commit(s) were added to refs/heads/master by this push:
new 629c85c5950 boards/arm/stm32h7: Add stm32h7s8-dk Ethernet support
629c85c5950 is described below
commit 629c85c5950fe371c83fd613da3da6d1b9a1e8a5
Author: Peter Barada <[email protected]>
AuthorDate: Sun Oct 18 10:00:08 2026 -0400
boards/arm/stm32h7: Add stm32h7s8-dk Ethernet support
Add jumbo-xip configuraiton that enables ethernet.
Add STM32_ETH_MDIO GPIO Kconfig option which enables GPIO emulation of
SMA clause-22 communication with PHY; required when JP6 is in default
poition. If GPIO emulation is not enabled, JP6 must be in alternate
position to allow SMA communication with LAN8742A PHY via ETHMAC.
Signed-off-by Peter Barada <[email protected]>
---
.../arm/stm32h7/boards/stm32h7s8-dk/index.rst | 80 ++++++-
arch/arm/src/common/stm32/Kconfig.eth | 6 +
arch/arm/src/stm32h7/CMakeLists.txt | 6 +-
arch/arm/src/stm32h7/Make.defs | 6 +-
arch/arm/src/stm32h7/stm32_ethernet.c | 18 +-
arch/arm/src/stm32h7/stm32_mdio_gpio.c | 255 +++++++++++++++++++++
arch/arm/src/stm32h7/stm32_mdio_gpio.h | 65 ++++++
.../stm32h7s8-dk/configs/jumbo-xip/defconfig | 88 +++++++
boards/arm/stm32h7/stm32h7s8-dk/include/board.h | 34 +++
9 files changed, 553 insertions(+), 5 deletions(-)
diff --git a/Documentation/platforms/arm/stm32h7/boards/stm32h7s8-dk/index.rst
b/Documentation/platforms/arm/stm32h7/boards/stm32h7s8-dk/index.rst
index ad8efe2bd4e..44ad5821317 100644
--- a/Documentation/platforms/arm/stm32h7/boards/stm32h7s8-dk/index.rst
+++ b/Documentation/platforms/arm/stm32h7/boards/stm32h7s8-dk/index.rst
@@ -20,8 +20,8 @@ This page describes the NuttX port for the `STMicro
SMT32H7S8-DK <https://www.st
Discovery kit. The board is based on the 600 MHz STM32H7S3L8
Cortex-M7 microcontroller.
-Flashing NSH image
-==================
+Flashing internal NSH image
+===========================
.. note::
nsh image is restricted in size to fit in and execute from
@@ -44,6 +44,60 @@ Program and verify the internal image, then reset the board::
The internal nsh image presents a shell on the ST-link console on startup.
+XIP Boot
+========
+
+The STM32H7S3L8 has 64 KB of internal flash. The board also carries a
+32 MB MX25UW25645G NOR flash on XSPI2, mapped at ``0x70000000``. Running
+NuttX from the external flash uses two images:
+
+* ``boot-xip`` runs from internal flash at ``0x08000000``.
+* ``nsh-xip`` executes in place from XSPI2 flash at ``0x70000000``.
+
+The bootloader configures the MX25UW25645G in octal STR memory-mapped mode,
+validates the initial stack pointer and reset vector, and starts the external
+image. Image management, rollback, integrity checking, and authentication
+are not currently provided.
+
+Flashing bootloader and external image
+======================================
+
+.. note::
+ The ``XSPI2_HSLV`` option byte must be set to ``1`` before using the
+ external flash. The option byte setting is persistent.
+
+Build the external image::
+
+ cmake -B build/nsh-xip -DBOARD_CONFIG=nucleo-h7s3l8:nsh-xip -GNinja
+ cmake --build build/nsh-xip
+
+Build the internal bootloader::
+
+ cmake -B build/boot-xip -DBOARD_CONFIG=nucleo-h7s3l8:boot-xip -GNinja
+ cmake --build build/boot-xip
+
+Install STM32CubeProgrammer and set ``CUBE_PROGRAMMER`` to the path of its
+command-line executable. The external loader is supplied by the
+STM32CubeProgrammer installation::
+
+ CUBE_PROGRAMMER=/path/to/STM32_Programmer_CLI
+ EXTERNAL_LOADER="$(dirname
"$CUBE_PROGRAMMER")/ExternalLoader/MX66UW1G45G_STM32H7S78-DK.stldr"
+
+Erase the external flash, then program and verify the XIP image::
+
+ "$CUBE_PROGRAMMER" --connect port=SWD mode=Normal --erase all \
+ -el "$EXTERNAL_LOADER"
+ "$CUBE_PROGRAMMER" --connect port=SWD mode=Normal \
+ --download build/nsh-xip/nuttx.bin 0x70000000 --verify \
+ --skipErase \
+ -el "$EXTERNAL_LOADER"
+
+Program and verify the internal bootloader, then reset the board::
+
+ "$CUBE_PROGRAMMER" --connect port=SWD reset=HWrst \
+ --download build/boot-xip/nuttx.bin 0x08000000 --verify --rst
+
+
Configurations
==============
@@ -61,3 +115,25 @@ Provides a basic NuttShell configuration in internal flash
and
includes support for on-board LEDs and user button. The default
console is the ST-LINK virtual COM port on USART4.
+nsh-xip
+-------
+
+Provides NuttShell, common diagnostic commands, and ``ostest``. The image is
+linked for execution from XSPI2 flash at ``0x70000000`` and requires an XIP
+bootloader in internal flash.
+
+jumbo-xip
+---------
+
+Much as ``nsh-xip``, but adds Ethernet networking. The IP address is obtained
by DHCP.
+
+.. note::
+ ``jumbo-xip`` enables CONFIG_STM32_ETH_GPIO_MDIO to communicate via
+ GPIO pins PB2 and PA2 with LAN8742A Ethernet transceiver on the board,
+ and requires jumper JP6 to be in its default setting. If JP6 is in
+ alternate position, CONFIG_STM32_ETH_GPIO_MDIO must be disabled.
+
+boot-xip
+--------
+
+Provides the internal-flash NuttX bootloader used to start the ``nsh-xip`` or
``jumbo-xip`` image.
diff --git a/arch/arm/src/common/stm32/Kconfig.eth
b/arch/arm/src/common/stm32/Kconfig.eth
index 517d9d0d303..b768fdf3b41 100644
--- a/arch/arm/src/common/stm32/Kconfig.eth
+++ b/arch/arm/src/common/stm32/Kconfig.eth
@@ -23,6 +23,12 @@ config STM32_PHYINIT
provide stm32_phyinitialize(); The STM32 Ethernet driver will
call this function
one time before it first uses the PHY.
+config STM32_ETH_MDIO_GPIO
+ bool "Use GPIO-based MDIO communications"
+ ---help---
+ Enable to use GPIO pins (and bit-bang clause-22 MDIO
+ communication) instead of the SMA module provided in MAC.
+
config STM32_MII
bool "Use MII interface"
---help---
diff --git a/arch/arm/src/stm32h7/CMakeLists.txt
b/arch/arm/src/stm32h7/CMakeLists.txt
index 769e81a1433..8ff834153bf 100644
--- a/arch/arm/src/stm32h7/CMakeLists.txt
+++ b/arch/arm/src/stm32h7/CMakeLists.txt
@@ -181,7 +181,11 @@ if(CONFIG_STM32_ETHMAC)
endif()
if(CONFIG_MDIO_BUS)
- list(APPEND SRCS stm32_mdio.c)
+ if(CONFIG_STM32_ETH_MDIO_GPIO)
+ list(APPEND SRCS stm32_mdio_gpio.c)
+ else()
+ list(APPEND SRCS stm32_mdio.c)
+ endif()
endif()
if(CONFIG_PM)
diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs
index 8c44408bcc4..66c2b6b96db 100644
--- a/arch/arm/src/stm32h7/Make.defs
+++ b/arch/arm/src/stm32h7/Make.defs
@@ -184,7 +184,11 @@ CHIP_CSRCS += stm32_ethernet.c
endif
ifeq ($(CONFIG_MDIO_BUS),y)
-CHIP_CSRCS += stm32_mdio.c
+ ifeq ($(CONFIG_STM32_ETH_MDIO_GPIO),y)
+ CHIP_CSRCS += stm32_mdio_gpio.c
+ else
+ CHIP_CSRCS += stm32_mdio.c
+ endif
endif
diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c
b/arch/arm/src/stm32h7/stm32_ethernet.c
index 76a3b97c74d..cbc4a867d37 100644
--- a/arch/arm/src/stm32h7/stm32_ethernet.c
+++ b/arch/arm/src/stm32h7/stm32_ethernet.c
@@ -88,7 +88,12 @@
#include "stm32_rcc.h"
#include "stm32_ethernet.h"
#include "stm32_uid.h"
-#include "stm32_mdio.h"
+
+#ifdef CONFIG_STM32_ETH_MDIO_GPIO
+# include "stm32_mdio_gpio.h"
+#else
+# include "stm32_mdio.h"
+#endif
#include <arch/board/board.h>
@@ -4037,8 +4042,13 @@ static inline void stm32_ethgpioconfig(struct
stm32_ethmac_s *priv)
/* MDC and MDIO are common to both modes */
# ifndef CONFIG_STM32_NO_PHY
+# ifdef CONFIG_STM32_ETH_MDIO_GPIO
+ stm32_configgpio(GPIO_ETH_MDC_GPIO);
+ stm32_configgpio(GPIO_ETH_MDIO_GPIO_OUT);
+# else
stm32_configgpio(GPIO_ETH_MDC);
stm32_configgpio(GPIO_ETH_MDIO);
+# endif
# endif
/* Set up the MII interface */
@@ -5126,7 +5136,13 @@ static inline int stm32_ethinitialize(int intf)
/* Initialize the MDIO device */
+#ifdef CONFIG_STM32_ETH_MDIO_GPIO
+ priv->mdio = stm32_mdiogpio_bus_initialize(GPIO_ETH_MDC_GPIO,
+ GPIO_ETH_MDIO_GPIO_OUT,
+ GPIO_ETH_MDIO_GPIO_IN);
+#else
priv->mdio = stm32_mdio_bus_initialize();
+#endif
if (!priv->mdio)
{
nerr("ERROR: Failed to initialize MDIO bus\n");
diff --git a/arch/arm/src/stm32h7/stm32_mdio_gpio.c
b/arch/arm/src/stm32h7/stm32_mdio_gpio.c
new file mode 100644
index 00000000000..7c0476bc629
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_mdio_gpio.c
@@ -0,0 +1,255 @@
+/****************************************************************************
+ * arch/arm/src/stm32h7/stm32_mdio_gpio.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/debug.h>
+#include <nuttx/mutex.h>
+#include <nuttx/nuttx.h>
+
+#include <nuttx/debug.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <inttypes.h>
+
+#include <nuttx/net/mdio.h>
+/* #include <arch/board/board.h> */
+
+#include "arm_internal.h"
+#include "chip.h"
+#include "hardware/stm32_ethernet.h"
+#include "stm32_gpio.h"
+#include "stm32_mdio_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#undef CONFIG_DEBUG_STM32_MDIO_GPIO_INFO
+#ifdef CONFIG_DEBUG_STM32_MDIO_GPIO_INFO
+#define mg_info _info
+#else
+#define mg_info _none
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct stm32_mdiogpio_lowerhalf_s
+{
+ struct mdio_lowerhalf_s base;
+ uint32_t mdc_out; /* MDC GPIO pin definition for output */
+ uint32_t mdio_out; /* MDIO GPIO pin definition for output */
+ uint32_t mdio_in; /* MDIO GPIO pin definition for input */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int stm32_c22_read(struct mdio_lowerhalf_s *dev, uint8_t phydev,
+ uint8_t regaddr, uint16_t *value);
+
+static int stm32_c22_write(struct mdio_lowerhalf_s *dev, uint8_t phydev,
+ uint8_t regaddr, uint16_t value);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+const struct mdio_ops_s g_stm32_mdiogpio_ops =
+{
+ .read = stm32_c22_read,
+ .write = stm32_c22_write,
+ .reset = NULL,
+};
+
+struct stm32_mdiogpio_lowerhalf_s g_stm32_mdiogpio_lowerhalf =
+{
+ .base =
+ {
+ .ops = &g_stm32_mdiogpio_ops
+ },
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#define MDIO_DELAY() up_udelay(2) /* delay between clock edges */
+
+#define MDC_HIGH(priv) stm32_gpiowrite(priv->mdc_out, true)
+#define MDC_LOW(priv) stm32_gpiowrite(priv->mdc_out, false)
+#define MDIO_WRITE(priv, val) stm32_gpiowrite(priv->mdio_out, (val))
+#define MDIO_READ(priv) stm32_gpioread(priv->mdio_in)
+#define MDIO_MODE_OUT(priv) stm32_configgpio(priv->mdio_out)
+#define MDIO_MODE_IN(priv) stm32_configgpio(priv->mdio_in)
+
+static void mdiogpio_write_bit(struct stm32_mdiogpio_lowerhalf_s *priv,
+ bool bit)
+{
+ MDIO_WRITE(priv, bit);
+ MDIO_DELAY();
+ MDC_HIGH(priv); /* rising MDC edge latches MDIO data */
+ MDIO_DELAY();
+ MDC_LOW(priv);
+}
+
+static bool mdiogpio_read_bit(struct stm32_mdiogpio_lowerhalf_s *priv)
+{
+ bool bit;
+
+ MDC_HIGH(priv); /* PHY drives data on rising edge */
+ MDIO_DELAY();
+ bit = MDIO_READ(priv);
+ MDC_LOW(priv);
+ MDIO_DELAY();
+
+ return bit;
+}
+
+static void mdiogpio_send_bits(struct stm32_mdiogpio_lowerhalf_s *priv,
+ uint32_t val, int count)
+{
+ for (int i = count - 1; i >= 0; i--)
+ {
+ mdiogpio_write_bit(priv, (val >> i) & 1);
+ }
+}
+
+static int stm32_c22_read(struct mdio_lowerhalf_s *dev, uint8_t phydev,
+ uint8_t regaddr, uint16_t *value)
+{
+ struct stm32_mdiogpio_lowerhalf_s *priv =
+ container_of(dev, struct stm32_mdiogpio_lowerhalf_s, base);
+ uint16_t data = 0;
+
+ if (!value)
+ {
+ return -EINVAL;
+ }
+
+ MDIO_MODE_OUT(priv);
+
+ mdiogpio_send_bits(priv, 0xffffffff, 32); /* 32-bit preamble */
+
+ mdiogpio_send_bits(priv, 0x1, 2); /* Start-of-frame */
+ mdiogpio_send_bits(priv, 0x2, 2); /* OP: Read */
+
+ mdiogpio_send_bits(priv, phydev & 0x1f, 5); /* PHY Address */
+ mdiogpio_send_bits(priv, regaddr & 0x1f, 5); /* PHY Register */
+
+ MDIO_MODE_IN(priv); /* Turnaround (TA): Release MDIO line; switch pin to
input */
+
+ mdiogpio_read_bit(priv); /* First TA bit (expect hi-Z) */
+
+ /* Read 16 bits of payload */
+
+ for (int i = 15; i >= 0; i--)
+ {
+ if (mdiogpio_read_bit(priv))
+ {
+ data |= (1 << i);
+ }
+ }
+
+ /* Extra clock cycle to clean up state */
+
+ MDC_HIGH(priv);
+ MDIO_DELAY();
+ MDC_LOW(priv);
+ MDIO_DELAY();
+
+ *value = data;
+ mg_info("PHY 0x%02X Reg 0x%02X -> 0x%04X\n", phydev, regaddr, data);
+ return OK;
+}
+
+static int stm32_c22_write(struct mdio_lowerhalf_s *dev, uint8_t phydev,
+ uint8_t regaddr, uint16_t value)
+{
+ struct stm32_mdiogpio_lowerhalf_s *priv =
+ container_of(dev, struct stm32_mdiogpio_lowerhalf_s, base);
+
+ mg_info("PHY 0x%02X Reg 0x%02X <- 0x%04X\n", phydev, regaddr, value);
+
+ MDIO_MODE_OUT(priv);
+
+ mdiogpio_send_bits(priv, 0xffffffff, 32); /* 32-bit preamble */
+
+ mdiogpio_send_bits(priv, 0x01, 2); /* Start-of-frame */
+ mdiogpio_send_bits(priv, 0x01, 2); /* OP: Write */
+
+ mdiogpio_send_bits(priv, phydev & 0x1f, 5); /* PHY Address */
+ mdiogpio_send_bits(priv, regaddr & 0x1f, 5); /* PHY Register */
+
+ mdiogpio_send_bits(priv, 0x02, 2); /* Turnaround; driven as '10' by master */
+
+ mdiogpio_send_bits(priv, value, 16); /* Write 16 bits of data */
+
+ MDIO_MODE_IN(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_mdiogpio_bus_initialize
+ *
+ * Description:
+ * Initialize the MDIO bus to emulate STA via GPIO pins
+ *
+ * Input Parameters:
+ * mdc_out - MDC GPIO pin definition for output
+ * mdio_out - MDIO GPIO pin definition for output
+ * mdio_in - MDIO GPIO pin definition for input
+ *
+ * Returned Value:
+ * Initialized MDIO GPIO bus structure or NULL on failure
+ *
+ ****************************************************************************/
+
+struct mdio_bus_s *stm32_mdiogpio_bus_initialize(uint32_t mdc_out,
+ uint32_t mdio_out,
+ uint32_t mdio_in)
+{
+ struct stm32_mdiogpio_lowerhalf_s *priv = &g_stm32_mdiogpio_lowerhalf;
+
+ mg_info("\n");
+
+ priv->mdc_out = mdc_out;
+ priv->mdio_out = mdio_out;
+ priv->mdio_in = mdio_in;
+
+ stm32_configgpio(priv->mdc_out);
+ stm32_configgpio(priv->mdio_out);
+
+ return mdio_register(&priv->base);
+}
diff --git a/arch/arm/src/stm32h7/stm32_mdio_gpio.h
b/arch/arm/src/stm32h7/stm32_mdio_gpio.h
new file mode 100644
index 00000000000..ff1ac6a8b0a
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_mdio_gpio.h
@@ -0,0 +1,65 @@
+/****************************************************************************
+ * arch/arm/src/stm32h7/stm32_mdio_gpio.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_STM32_MDIO_GPIO_H
+#define __ARCH_ARM_SRC_STM32H7_STM32_MDIO_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/net/mdio.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_mdiogpio_bus_initialize
+ *
+ * Description:
+ * Initialize the MDIO bus to emilate STA via GPIO pins
+ *
+ * Input Parameters:
+ * mdc_out - MDC GPIO pin definition for output
+ * mdio_out - MDIO GPIO pin definition for output
+ * mdio_in - MDIO GPIO pin definition for input
+ *
+ * Returned Value:
+ * Initialized MDIO GPIO bus structure or NULL on failure
+ *
+ ****************************************************************************/
+
+struct mdio_bus_s *stm32_mdiogpio_bus_initialize(uint32_t mdc_out,
+ uint32_t mdio_out,
+ uint32_t mdio_inp);
+
+#endif /* __ARCH_ARM_SRC_STM32H7_STM32_MDIO_GPIO_H */
diff --git a/boards/arm/stm32h7/stm32h7s8-dk/configs/jumbo-xip/defconfig
b/boards/arm/stm32h7/stm32h7s8-dk/configs/jumbo-xip/defconfig
new file mode 100644
index 00000000000..9117d5f28dd
--- /dev/null
+++ b/boards/arm/stm32h7/stm32h7s8-dk/configs/jumbo-xip/defconfig
@@ -0,0 +1,88 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed
.config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that
includes your
+# modifications.
+#
+# CONFIG_ARCH_LEDS is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="stm32h7s8-dk"
+CONFIG_ARCH_BOARD_STM32H7S8_DK=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP="stm32h7"
+CONFIG_ARCH_CHIP_STM32=y
+CONFIG_ARCH_CHIP_STM32H7=y
+CONFIG_ARCH_CHIP_STM32H7S3L8=y
+CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y
+CONFIG_ARCH_IRQBUTTONS=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_BOARD_LOOPSPERMSEC=119965
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_SYMBOLS_LEVEL="-g3"
+CONFIG_ETH0_PHY_LAN8742A=y
+CONFIG_EXAMPLES_BUTTONS=y
+CONFIG_EXAMPLES_BUTTONS_NAMES=y
+CONFIG_EXAMPLES_BUTTONS_QTD=1
+CONFIG_EXAMPLES_LEDS=y
+CONFIG_EXAMPLES_TELNETD=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_FS_TMPFS=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INPUT=y
+CONFIG_INPUT_BUTTONS=y
+CONFIG_INPUT_BUTTONS_LOWER=y
+CONFIG_INPUT_GOLDFISH_EVENTS=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_NET=y
+CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_THREAD=y
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NET_ETH_PKTSIZE=1500
+CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_STATISTICS=y
+CONFIG_NET_TCP=y
+CONFIG_NET_UDP=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_MAXARGUMENTS=16
+CONFIG_NSH_READLINE=y
+CONFIG_PIPES=y
+CONFIG_RAM_SIZE=466944
+CONFIG_RAM_START=0x24000000
+CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=22
+CONFIG_START_MONTH=9
+CONFIG_START_YEAR=2026
+CONFIG_STM32H7S8_DK_XIP=y
+CONFIG_STM32_ETHMAC=y
+CONFIG_STM32_ETH_MDIO_GPIO=y
+CONFIG_STM32_PHYSR=31
+CONFIG_STM32_PHYSR_100FD=0x0018
+CONFIG_STM32_PHYSR_100HD=0x0008
+CONFIG_STM32_PHYSR_10FD=0x0014
+CONFIG_STM32_PHYSR_10HD=0x0004
+CONFIG_STM32_PHYSR_ALTCONFIG=y
+CONFIG_STM32_PHYSR_ALTMODE=0x001c
+CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y
+CONFIG_STM32_UART4=y
+CONFIG_SYSTEM_DHCPC_RENEW=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_PING=y
+CONFIG_TESTING_OSTEST=y
+CONFIG_UART4_SERIAL_CONSOLE=y
+CONFIG_USERLED=y
+CONFIG_USERLED_LOWER=y
diff --git a/boards/arm/stm32h7/stm32h7s8-dk/include/board.h
b/boards/arm/stm32h7/stm32h7s8-dk/include/board.h
index 7c8125f0f68..1b475219c47 100644
--- a/boards/arm/stm32h7/stm32h7s8-dk/include/board.h
+++ b/boards/arm/stm32h7/stm32h7s8-dk/include/board.h
@@ -226,4 +226,38 @@
#define GPIO_XSPI2_IO6 (GPIO_XSPI2_IO6_1 | GPIO_SPEED_100MHz)
#define GPIO_XSPI2_IO7 (GPIO_XSPI2_IO7_1 | GPIO_SPEED_100MHz)
+/* Ethernet: LAN8742A PHY on RMII, RJ45 at CN10. */
+
+/* SMA clause-22 communication with PHY can be handled in two ways:
+ * - SMA hardware internal to ETHMAC
+ * - emulated via GPIO pins
+ * On STM32H7S8-DK JP6 in its default setting connects MDC to PB2
+ * requiring SMA emulation via GPIO pins.
+ * JP6 in alternate setting connects MDC to PC1 which can be muxed
+ * as ETH_MDC signal allowing either SMA hardware or GPIO emulation.
+ * For GPIO SMA emilation, note two definitions for MDIO pin,
+ * one for input(PHY->STM32), and other for output(STM32->PHY).
+ */
+
+#ifdef CONFIG_STM32_ETH_MDIO_GPIO
+#define GPIO_ETH_MDC_GPIO (GPIO_OUTPUT | GPIO_PUSHPULL \
+ | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR \
+ | GPIO_PORTB | GPIO_PIN2)
/* PB2 */
+#define GPIO_ETH_MDIO_GPIO_OUT (GPIO_OUTPUT | GPIO_OPENDRAIN \
+ | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN2)
/* PA2 */
+#define GPIO_ETH_MDIO_GPIO_IN (GPIO_INPUT | GPIO_FLOAT \
+ | GPIO_PORTA | GPIO_PIN2)
/* PA2 */
+#else
+#define GPIO_ETH_MDC (GPIO_ETH_MDC_1 | GPIO_SPEED_100MHz)
/* PC1 */
+#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_1 | GPIO_SPEED_100MHz)
/* PA2 */
+#endif
+
+#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_3 | GPIO_SPEED_100MHz)
/* PD7 */
+#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_1 | GPIO_SPEED_100MHz)
/* PA7 */
+#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_1 | GPIO_SPEED_100MHz)
/* PC4 */
+#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_1 | GPIO_SPEED_100MHz)
/* PC5 */
+#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_3 | GPIO_SPEED_100MHz)
/* PG11 */
+#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_1 | GPIO_SPEED_100MHz)
/* PB0 */
+#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1 | GPIO_SPEED_100MHz)
/* PB1 */
+
#endif /* __BOARDS_ARM_STM32H7_STM32H7S8_DK_INCLUDE_BOARD_H */
