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commit 87e653fbb409ba172403c6170d763581d2dc244c Author: Marco Casaroli <[email protected]> AuthorDate: Mon Oct 19 22:16:50 2026 +0200 Revert "arm64: cache TLS info pointer in TPIDR_EL0" This reverts commit 5cfe424bc3f84c30b56cb3b67230462d1e1d140f. The commit defines up_tls_info() as a read of TPIDR_EL0 also for the kernel, so tls_get_info() in the kernel takes the TLS info from a register that user code can write. In a protected or a kernel build, the kernel then writes errno to an address that user code selects: a test program that points TPIDR_EL0 to a copy of its TLS info and calls open() on a missing file sees the kernel write ENOENT into the copy ("kernel wrote errno through the user TPIDR_EL0 YES" on qemu-armv8a:knsh). With CONFIG_TLS_NCLEANUP > 0, tls_cleanup_push() also writes a callback and its argument there. The commit also writes stack_alloc_ptr to TPIDR_EL0 at each context switch, so a value that user code writes is lost. The revert keeps the blank line that the commit added in arm64_cpustart.c, which nxstyle needs. The next commit keeps TPIDR_EL0 per thread in the context instead, and only user code reads it. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Marco Casaroli <[email protected]> --- arch/arm64/include/irq.h | 1 - arch/arm64/src/common/arm64_boot.c | 1 - arch/arm64/src/common/arm64_cpustart.c | 2 -- arch/arm64/src/common/arm64_doirq.c | 4 ---- arch/arm64/src/common/arm64_head.S | 6 ++---- arch/arm64/src/common/arm64_internal.h | 13 ------------- arch/arm64/src/common/arm64_syscall.c | 5 ----- 7 files changed, 2 insertions(+), 30 deletions(-) diff --git a/arch/arm64/include/irq.h b/arch/arm64/include/irq.h index a3a14ad9f92..e38d46c5bd8 100644 --- a/arch/arm64/include/irq.h +++ b/arch/arm64/include/irq.h @@ -493,7 +493,6 @@ static inline_function void up_irq_restore(irqstate_t flags) #define up_this_task() ((struct tcb_s *)(read_sysreg(tpidr_el1) & ~1ul)) #define up_update_task(t) modify_sysreg(t, ~1ul, tpidr_el1) #define up_interrupt_context() (read_sysreg(tpidr_el1) & 1) -#define up_tls_info() ((struct tls_info_s *)read_sysreg(tpidr_el0)) #define up_switch_context(tcb, rtcb) \ do \ diff --git a/arch/arm64/src/common/arm64_boot.c b/arch/arm64/src/common/arm64_boot.c index cea799e62e8..1dfacf867d4 100644 --- a/arch/arm64/src/common/arm64_boot.c +++ b/arch/arm64/src/common/arm64_boot.c @@ -238,7 +238,6 @@ void arm64_boot_el1_init(void) void arm64_boot_primary_c_routine(void) { - arm64_tp_boot(0); arm64_chip_boot(); nx_start(); } diff --git a/arch/arm64/src/common/arm64_cpustart.c b/arch/arm64/src/common/arm64_cpustart.c index d2ced2fa756..42a41c7fe36 100644 --- a/arch/arm64/src/common/arm64_cpustart.c +++ b/arch/arm64/src/common/arm64_cpustart.c @@ -216,8 +216,6 @@ int up_cpu_start(int cpu) void arm64_boot_secondary_c_routine(void) { - arm64_tp_boot(this_cpu()); - #ifdef CONFIG_ARCH_HAVE_MPU arm64_mpu_init(false); #endif diff --git a/arch/arm64/src/common/arm64_doirq.c b/arch/arm64/src/common/arm64_doirq.c index 3e93419473c..c1fe07d1f04 100644 --- a/arch/arm64/src/common/arm64_doirq.c +++ b/arch/arm64/src/common/arm64_doirq.c @@ -135,10 +135,6 @@ uint64_t *arm64_doirq(int irq, uint64_t * regs) nxsched_switch_context(*running_task, tcb); - /* Update the TLS pointer */ - - write_sysreg(tcb->stack_alloc_ptr, tpidr_el0); - /* Record the new "running" task when context switch occurred. * g_running_tasks[] is only used by assertion logic for reporting * crashes. diff --git a/arch/arm64/src/common/arm64_head.S b/arch/arm64/src/common/arm64_head.S index 1c6c3752a5e..d219cf6c4dc 100644 --- a/arch/arm64/src/common/arm64_head.S +++ b/arch/arm64/src/common/arm64_head.S @@ -181,10 +181,9 @@ real_start: add x24, x24, #(SMP_STACK_SIZE) # endif - /* Initialize percpu reg tpidr_el1 tpidr_el0 */ + /* Initialize percpu reg tpidr_el1 */ msr tpidr_el1, xzr - msr tpidr_el0, xzr ldr x25, =arm64_boot_secondary_c_routine bl __reset_prep_c @@ -210,10 +209,9 @@ primary_core: ldr x24, =(g_idle_stack + CONFIG_IDLETHREAD_STACKSIZE) #endif /* CONFIG_SMP */ - /* Initialize percpu reg tpidr_el1 tpidr_el0 */ + /* Initialize percpu reg tpidr_el1 */ msr tpidr_el1, xzr - msr tpidr_el0, xzr ldr x25, =arm64_boot_primary_c_routine /* Prepare for calling C code */ diff --git a/arch/arm64/src/common/arm64_internal.h b/arch/arm64/src/common/arm64_internal.h index c76d2a17c61..52f53be16a7 100644 --- a/arch/arm64/src/common/arm64_internal.h +++ b/arch/arm64/src/common/arm64_internal.h @@ -392,19 +392,6 @@ void arm64_stack_color(void *stackbase, size_t nbytes); void arm64_enable_dbgmonitor(void); #endif -static inline_function void arm64_tp_boot(int cpu) -{ - uintptr_t val; - -#ifdef CONFIG_SMP - val = (uintptr_t)(g_cpu_idlestackalloc[cpu]); -#else - val = (uintptr_t)(g_idle_stack); -#endif - - write_sysreg(val, tpidr_el0); -} - #undef EXTERN #ifdef __cplusplus } diff --git a/arch/arm64/src/common/arm64_syscall.c b/arch/arm64/src/common/arm64_syscall.c index 2bc6712f592..312444b018b 100644 --- a/arch/arm64/src/common/arm64_syscall.c +++ b/arch/arm64/src/common/arm64_syscall.c @@ -360,10 +360,5 @@ uint64_t *arm64_syscall(uint64_t *regs) /* Clear irq flag */ write_sysreg((uintptr_t)tcb & ~1ul, tpidr_el1); - - /* Update the TLS pointer */ - - write_sysreg(tcb->stack_alloc_ptr, tpidr_el0); - return regs; }
