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commit 0e9bb1915e765a734fb4771cd6e16155e908875e Author: Marco Casaroli <[email protected]> AuthorDate: Tue Oct 20 14:25:31 2026 +0200 arch/arm64: Wait for the instruction cache invalidation. up_invalidate_icache_all() ran IC IALLUIS, and up_invalidate_icache() ran IC IVAU for each line, without a DSB after it. The architecture completes a cache maintenance instruction only at the next DSB, so the CPU could still fetch old instructions after the call. For example a program that wrote new code into a page and made it executable with mprotect() sometimes ran the old code. Add DSB and ISB after the invalidation. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Marco Casaroli <[email protected]> --- arch/arm64/src/common/arm64_cache.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/src/common/arm64_cache.c b/arch/arm64/src/common/arm64_cache.c index 0ae9ba57b8a..25a456e945c 100644 --- a/arch/arm64/src/common/arm64_cache.c +++ b/arch/arm64/src/common/arm64_cache.c @@ -389,6 +389,11 @@ size_t up_get_icache_size(void) void up_invalidate_icache_all(void) { __ic_ialluis(); + + /* Wait until the invalidation is done before the next fetch */ + + UP_DSB(); + UP_ISB(); } /**************************************************************************** @@ -423,6 +428,7 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end) start += line_size; } + UP_DSB(); UP_ISB(); }
