AlexKlimaj opened a new pull request, #20910: URL: https://github.com/apache/nuttx/pull/20910
*Note: Please adhere to [Contributing Guidelines](https://github.com/apache/nuttx/blob/master/CONTRIBUTING.md).* ## Summary * Since #12317 (975d99c3f61), `mmcsd_sdinitialize()` switches an SD card to the 4-bit bus only when the host reports `SDIO_CAPS_4BIT`. The STM32 SDIO and SDMMC drivers never report it, so SD cards on STM32 stay on the 1-bit bus even when the slot is wired for 4-bit and the card supports it. #13861 fixed the same problem for cxd56xx. * `stm32_capabilities()` now reports `SDIO_CAPS_4BIT` unless the slot is limited to 1-bit operation: `CONFIG_STM32_SDIO_WIDTH_D1_ONLY` on F1/F2/F4, `CONFIG_SDMMCn_WIDTH_D1_ONLY` on the F7, H5, H7 and L4 SDMMC drivers. `mmcsd_widebus()` still checks the card's SCR before selecting 4-bit. * The first commit fixes the nxstyle errors already present in the F1/F2/F4, F7 and L4 drivers, so the series passes checkpatch. It changes only whitespace, apart from declaring `result` before `DEBUGASSERT()` in each `stm32_dmacallback()`. * Other host drivers that report neither `SDIO_CAPS_4BIT` nor `SDIO_CAPS_4BIT_ONLY` select 1-bit for the same reason and are not changed here: at32, kinetis, lpc17xx_40xx, lpc43xx, lpc54xx, sam34, sama5 (HSMCI), samv7, mpfs (eMMCSD), esp32s3, and gd32f4 when `CONFIG_GD32F4_SDIO_DMA` is set. ## Impact * New feature: NO. * User: YES. SD cards on STM32 boards with a 4-bit slot run on the 4-bit bus again; on an STM32H743, sequential write throughput goes from 1.1 to 1.9 MB/s with 4 KiB writes and from 1.5 to 3.0–4.1 MB/s with 16 KiB writes. * Build: NO. * Hardware: YES. The STM32 F1/F2/F4 SDIO driver and the F7, H5, H7 and L4 SDMMC drivers. A board whose slot is wired for 1-bit only must select the existing `*_WIDTH_D1_ONLY` option. * Documentation: NO. * Security: NO. * Compatibility: NO API or configuration change. ## Testing * Build host: Ubuntu 24.04.5, Linux 7.0.0 x86_64, Intel Core i5-14400F, arm-none-eabi-gcc 13.2.1, CMake 3.28.3 with Ninja. * Build, on this branch: `weact-stm32h743:sdcard` (H7), `stm32f746-ws:nsh` (F7) and `stm3240g-eval:nsh2` (F4) build cleanly. No in-tree defconfig enables SDMMC on H5 or L4. With `STM32_SDMMC1` forced on for `nucleo-h563zi:nsh` and `nucleo-l496zg:nsh`, both drivers compile up to the SDMMC pin and clock macros those boards do not define, which are unrelated to this change. * Runtime target: ARK FPV flight controller, STM32H743IIK6, 64 GB SD card on SDMMC2, 4-bit wiring. It runs PX4 firmware on PX4's NuttX 12.12.0-based branch, which has the same `mmcsd_sdinitialize()` gate and `stm32_capabilities()` as master. There is no upstream board configuration for this hardware, so the runtime test used that branch with this commit cherry-picked. * Method: PX4's `sd_bench` sequential write test (5 runs of 2 s by default), plus `SDMMC2_CLKCR` read live over SWD at 0x48022404. Build logs (CMake + Ninja, this branch): ``` $ cmake -B b-h7 -GNinja -DBOARD_CONFIG=weact-stm32h743:sdcard && cmake --build b-h7 Building C object arch/CMakeFiles/arch.dir/arm/src/stm32h7/stm32_sdmmc.c.o [1381/1381] Generating System.map $ cmake -B b-f7 -GNinja -DBOARD_CONFIG=stm32f746-ws:nsh && cmake --build b-f7 Building C object arch/CMakeFiles/arch.dir/arm/src/stm32f7/stm32_sdmmc.c.o [1228/1228] Generating System.map $ cmake -B b-f4 -GNinja -DBOARD_CONFIG=stm3240g-eval:nsh2 && cmake --build b-f4 Building C object arch/CMakeFiles/arch.dir/arm/src/common/stm32/stm32_sdio_m3m4_v1.c.o [1437/1437] Generating System.map $ ./tools/checkpatch.sh -c -u -m -g HEAD~2..HEAD (clean) ``` Testing logs before change (`WIDBUS` = 00, 1-bit): ``` $ st-flash --hot-plug read clkcr.bin 0x48022404 4 -> SDMMC2_CLKCR = 0x00031005 nsh> sd_bench INFO [sd_bench] Using block size = 4096 bytes, sync=0 INFO [sd_bench] Testing Sequential Write Speed... INFO [sd_bench] Run 0: 980.11 KB/s, max write time: 44 ms (= 90.91 KB/s), fsync: 4 ms INFO [sd_bench] Run 1: 1220.38 KB/s, max write time: 42 ms (= 95.24 KB/s), fsync: 8 ms INFO [sd_bench] Run 2: 1309.09 KB/s, max write time: 8 ms (= 500.00 KB/s), fsync: 4 ms INFO [sd_bench] Run 3: 1167.71 KB/s, max write time: 9 ms (= 444.44 KB/s), fsync: 4 ms INFO [sd_bench] Run 4: 1005.65 KB/s, max write time: 52 ms (= 76.92 KB/s), fsync: 6 ms INFO [sd_bench] Avg : 1136.58 KB/s nsh> sd_bench -b 16384 -r 3 INFO [sd_bench] Avg : 1521.00 KB/s ``` Testing logs after change (`WIDBUS` = 01, 4-bit): ``` $ st-flash --hot-plug read clkcr.bin 0x48022404 4 -> SDMMC2_CLKCR = 0x00035005 nsh> sd_bench INFO [sd_bench] Using block size = 4096 bytes, sync=0 INFO [sd_bench] Testing Sequential Write Speed... INFO [sd_bench] Run 0: 2215.18 KB/s, max write time: 41 ms (= 97.56 KB/s), fsync: 5 ms INFO [sd_bench] Run 1: 2300.40 KB/s, max write time: 10 ms (= 400.00 KB/s), fsync: 4 ms INFO [sd_bench] Run 2: 1982.19 KB/s, max write time: 50 ms (= 80.00 KB/s), fsync: 4 ms INFO [sd_bench] Run 3: 1657.12 KB/s, max write time: 39 ms (= 102.56 KB/s), fsync: 4 ms INFO [sd_bench] Run 4: 1599.70 KB/s, max write time: 38 ms (= 105.26 KB/s), fsync: 5 ms INFO [sd_bench] Avg : 1949.77 KB/s nsh> sd_bench -b 16384 -r 3 INFO [sd_bench] Avg : 3410.11 KB/s nsh> sd_bench -v -r 3 INFO [sd_bench] Testing Sequential Read Speed of 2707 blocks INFO [sd_bench] Avg : 4203.97 KB/s 2707 blocks read and verified ``` ## PR verification Self-Check * [x] This PR introduces only one functional change. * [x] I have updated all required description fields above. * [x] My PR adheres to Contributing [Guidelines](https://github.com/apache/nuttx/blob/master/CONTRIBUTING.md) and [Documentation](https://nuttx.apache.org/docs/latest/contributing/index.html) (git commit title and message, coding standard, etc). * [ ] My PR is still work in progress (not ready for review). * [x] My PR is ready for review and can be safely merged into a codebase. -- This is an automated message from the Apache Git Service. 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