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commit 9d95130279b020b718150517975659990d528ad7 Author: alexklimaj <[email protected]> AuthorDate: Thu Oct 22 17:13:43 2026 -0600 arch/arm/stm32: Fix nxstyle errors in the SDIO and SDMMC drivers. Fix the existing nxstyle errors in the F1/F2/F4, F7 and L4 SDIO and SDMMC drivers, so that the 4-bit capability change that follows passes checkpatch: * indent statements and switch cases to the enclosing brace. * add the missing blank lines after declarations. * in stm32_dmacallback(), declare result before DEBUGASSERT(). No functional change. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: alexklimaj <[email protected]> --- arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c | 94 +++++++++--------- arch/arm/src/stm32f7/stm32_sdmmc.c | 123 ++++++++++++------------ arch/arm/src/stm32l4/stm32l4_sdmmc.c | 127 +++++++++++++------------ 3 files changed, 176 insertions(+), 168 deletions(-) diff --git a/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c index e14de3221ca..b0fc0701e80 100644 --- a/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c @@ -902,9 +902,10 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; - DEBUGASSERT(priv->dmamode); sdio_eventset_t result; + DEBUGASSERT(priv->dmamode); + /* In the normal case, SDIO appears to handle the End-Of-Transfer interrupt * first with the End-Of-DMA event occurring significantly later. On * transfer errors, however, the DMA error will occur before the End-of- @@ -1157,7 +1158,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) for (i = 0; i < (int)priv->remaining; i++) { - *ptr++ = data.b[i]; + *ptr++ = data.b[i]; } /* Now the transfer is finished */ @@ -1713,6 +1714,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) static sdio_statset_t stm32_status(struct sdio_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + return priv->cdstatus; } @@ -1885,23 +1887,23 @@ static int stm32_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, switch (cmd & MMCSD_RESPONSE_MASK) { - case MMCSD_NO_RESPONSE: - regval |= SDIO_CMD_NORESPONSE; - break; - - case MMCSD_R1_RESPONSE: - case MMCSD_R1B_RESPONSE: - case MMCSD_R3_RESPONSE: - case MMCSD_R4_RESPONSE: - case MMCSD_R5_RESPONSE: - case MMCSD_R6_RESPONSE: - case MMCSD_R7_RESPONSE: - regval |= SDIO_CMD_SHORTRESPONSE; - break; - - case MMCSD_R2_RESPONSE: - regval |= SDIO_CMD_LONGRESPONSE; - break; + case MMCSD_NO_RESPONSE: + regval |= SDIO_CMD_NORESPONSE; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R3_RESPONSE: + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + case MMCSD_R7_RESPONSE: + regval |= SDIO_CMD_SHORTRESPONSE; + break; + + case MMCSD_R2_RESPONSE: + regval |= SDIO_CMD_LONGRESPONSE; + break; } /* Set CPSMEN and the command index */ @@ -2161,29 +2163,29 @@ static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) switch (cmd & MMCSD_RESPONSE_MASK) { - case MMCSD_NO_RESPONSE: - events = SDIO_CMDDONE_STA; - timeout = MSEC2TICK(SDIO_CMDTIMEOUT_MS); - break; - - case MMCSD_R1_RESPONSE: - case MMCSD_R1B_RESPONSE: - case MMCSD_R2_RESPONSE: - case MMCSD_R4_RESPONSE: - case MMCSD_R5_RESPONSE: - case MMCSD_R6_RESPONSE: - events = SDIO_RESPDONE_STA; - timeout = MSEC2TICK(SDIO_LONGTIMEOUT_MS); - break; - - case MMCSD_R3_RESPONSE: - case MMCSD_R7_RESPONSE: - events = SDIO_RESPDONE_STA; - timeout = MSEC2TICK(SDIO_CMDTIMEOUT_MS); - break; - - default: - return -EINVAL; + case MMCSD_NO_RESPONSE: + events = SDIO_CMDDONE_STA; + timeout = MSEC2TICK(SDIO_CMDTIMEOUT_MS); + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R2_RESPONSE: + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + events = SDIO_RESPDONE_STA; + timeout = MSEC2TICK(SDIO_LONGTIMEOUT_MS); + break; + + case MMCSD_R3_RESPONSE: + case MMCSD_R7_RESPONSE: + events = SDIO_RESPDONE_STA; + timeout = MSEC2TICK(SDIO_CMDTIMEOUT_MS); + break; + + default: + return -EINVAL; } /* Then wait for the response (or timeout) */ @@ -2988,10 +2990,10 @@ static void stm32_callback(void *arg) { /* Yes.. queue it */ - mcinfo("Queuing callback to %p(%p)\n", - priv->callback, priv->cbarg); - work_queue(HPWORK, &priv->cbwork, priv->callback, - priv->cbarg, 0); + mcinfo("Queuing callback to %p(%p)\n", + priv->callback, priv->cbarg); + work_queue(HPWORK, &priv->cbwork, priv->callback, + priv->cbarg, 0); } else { diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index debd8c2b704..8be87aae602 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -901,6 +901,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask) { irqstate_t flags; + flags = enter_critical_section(); priv->xfrmask = xfrmask; @@ -1114,9 +1115,10 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; - DEBUGASSERT(priv->dmamode); sdio_eventset_t result; + DEBUGASSERT(priv->dmamode); + /* In the normal case, SDIO appears to handle the End-Of-Transfer interrupt * first with the End-Of-DMA event occurring significantly later. On * transfer errors, however, the DMA error will occur before the End-of- @@ -1332,7 +1334,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) /* Put the word in the FIFO */ - sdmmc_putreg32(priv, data.w, STM32_SDMMC_FIFO_OFFSET); + sdmmc_putreg32(priv, data.w, STM32_SDMMC_FIFO_OFFSET); } } @@ -1385,7 +1387,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) for (i = 0; i < (int)priv->remaining; i++) { - *ptr++ = data.b[i]; + *ptr++ = data.b[i]; } /* Now the transfer is finished */ @@ -1766,9 +1768,9 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) { /* Yes.. wake the thread up */ - sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | - STM32_SDMMC_CMDDONE_ICR, - STM32_SDMMC_ICR_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | + STM32_SDMMC_CMDDONE_ICR, + STM32_SDMMC_ICR_OFFSET); stm32_endwait(priv, SDIOWAIT_RESPONSEDONE); } } @@ -1783,8 +1785,8 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) { /* Yes.. wake the thread up */ - sdmmc_putreg32(priv, STM32_SDMMC_CMDDONE_ICR, - STM32_SDMMC_ICR_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_CMDDONE_ICR, + STM32_SDMMC_ICR_OFFSET); stm32_endwait(priv, SDIOWAIT_CMDDONE); } } @@ -1971,6 +1973,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) static sdio_statset_t stm32_status(struct sdio_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + return priv->cdstatus; } @@ -2101,10 +2104,10 @@ static int stm32_attach(struct sdio_dev_s *dev) * interrupt flags */ - sdmmc_putreg32(priv, STM32_SDMMC_MASK_RESET, - STM32_SDMMC_MASK_OFFSET); - sdmmc_putreg32(priv, STM32_SDMMC_ICR_STATICFLAGS, - STM32_SDMMC_ICR_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_MASK_RESET, + STM32_SDMMC_MASK_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_ICR_STATICFLAGS, + STM32_SDMMC_ICR_OFFSET); /* Enable SDIO interrupts at the NVIC. They can now be enabled at * the SDIO controller as needed. @@ -2154,23 +2157,23 @@ static int stm32_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, switch (cmd & MMCSD_RESPONSE_MASK) { - case MMCSD_NO_RESPONSE: - regval |= STM32_SDMMC_CMD_NORESPONSE; - break; - - case MMCSD_R1_RESPONSE: - case MMCSD_R1B_RESPONSE: - case MMCSD_R3_RESPONSE: - case MMCSD_R4_RESPONSE: - case MMCSD_R5_RESPONSE: - case MMCSD_R6_RESPONSE: - case MMCSD_R7_RESPONSE: - regval |= STM32_SDMMC_CMD_SHORTRESPONSE; - break; - - case MMCSD_R2_RESPONSE: - regval |= STM32_SDMMC_CMD_LONGRESPONSE; - break; + case MMCSD_NO_RESPONSE: + regval |= STM32_SDMMC_CMD_NORESPONSE; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R3_RESPONSE: + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + case MMCSD_R7_RESPONSE: + regval |= STM32_SDMMC_CMD_SHORTRESPONSE; + break; + + case MMCSD_R2_RESPONSE: + regval |= STM32_SDMMC_CMD_LONGRESPONSE; + break; } /* Set CPSMEN and the command index */ @@ -2410,29 +2413,29 @@ static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) switch (cmd & MMCSD_RESPONSE_MASK) { - case MMCSD_NO_RESPONSE: - events = STM32_SDMMC_CMDDONE_STA; - timeout = SDMMC_CMDTIMEOUT; - break; - - case MMCSD_R1_RESPONSE: - case MMCSD_R1B_RESPONSE: - case MMCSD_R2_RESPONSE: - case MMCSD_R4_RESPONSE: - case MMCSD_R5_RESPONSE: - case MMCSD_R6_RESPONSE: - events = STM32_SDMMC_RESPDONE_STA; - timeout = SDMMC_LONGTIMEOUT; - break; - - case MMCSD_R3_RESPONSE: - case MMCSD_R7_RESPONSE: - events = STM32_SDMMC_RESPDONE_STA; - timeout = SDMMC_CMDTIMEOUT; - break; - - default: - return -EINVAL; + case MMCSD_NO_RESPONSE: + events = STM32_SDMMC_CMDDONE_STA; + timeout = SDMMC_CMDTIMEOUT; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R2_RESPONSE: + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + events = STM32_SDMMC_RESPDONE_STA; + timeout = SDMMC_LONGTIMEOUT; + break; + + case MMCSD_R3_RESPONSE: + case MMCSD_R7_RESPONSE: + events = STM32_SDMMC_RESPDONE_STA; + timeout = SDMMC_CMDTIMEOUT; + break; + + default: + return -EINVAL; } /* Then wait for the response (or timeout) */ @@ -2441,9 +2444,9 @@ static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) { if (--timeout <= 0) { - mcerr("ERROR: Timeout cmd: %08" PRIx32 - " events: %08" PRIx32 " STA: %08" PRIx32 "\n", - cmd, events, sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET)); + mcerr("ERROR: Timeout cmd: %08" PRIx32 + " events: %08" PRIx32 " STA: %08" PRIx32 "\n", + cmd, events, sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET)); return -ETIMEDOUT; } @@ -2743,7 +2746,7 @@ static void stm32_waitenable(struct sdio_dev_s *dev, /* Enable event-related interrupts */ - sdmmc_putreg32(priv, STM32_SDMMC_WAITALL_ICR, STM32_SDMMC_ICR_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_WAITALL_ICR, STM32_SDMMC_ICR_OFFSET); } stm32_configwaitints(priv, waitmask, eventset, 0); @@ -3272,10 +3275,10 @@ static void stm32_callback(void *arg) { /* Yes.. queue it */ - mcinfo("Queuing callback to %p(%p)\n", - priv->callback, priv->cbarg); - work_queue(HPWORK, &priv->cbwork, priv->callback, - priv->cbarg, 0); + mcinfo("Queuing callback to %p(%p)\n", + priv->callback, priv->cbarg); + work_queue(HPWORK, &priv->cbwork, priv->callback, + priv->cbarg, 0); } else { diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index e0eb3e327b8..ef61898b6d0 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -1009,9 +1009,10 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; - DEBUGASSERT(priv->dmamode); sdio_eventset_t result; + DEBUGASSERT(priv->dmamode); + /* In the normal case, SDIO appears to handle the End-Of-Transfer interrupt * first with the End-Of-DMA event occurring significantly later. On * transfer errors, however, the DMA error will occur before the End-of- @@ -1196,7 +1197,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) /* Put the word in the FIFO */ - sdmmc_putreg32(priv, data.w, STM32_SDMMC_FIFO_OFFSET); + sdmmc_putreg32(priv, data.w, STM32_SDMMC_FIFO_OFFSET); } } @@ -1249,7 +1250,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) for (i = 0; i < (int)priv->remaining; i++) { - *ptr++ = data.b[i]; + *ptr++ = data.b[i]; } /* Now the transfer is finished */ @@ -1594,9 +1595,9 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) { /* Yes.. wake the thread up */ - sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | - STM32_SDMMC_CMDDONE_ICR, - STM32_SDMMC_ICR_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | + STM32_SDMMC_CMDDONE_ICR, + STM32_SDMMC_ICR_OFFSET); stm32_endwait(priv, SDIOWAIT_RESPONSEDONE); } } @@ -1611,8 +1612,8 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) { /* Yes.. wake the thread up */ - sdmmc_putreg32(priv, STM32_SDMMC_CMDDONE_ICR, - STM32_SDMMC_ICR_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_CMDDONE_ICR, + STM32_SDMMC_ICR_OFFSET); stm32_endwait(priv, SDIOWAIT_CMDDONE); } } @@ -1766,6 +1767,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) static sdio_statset_t stm32_status(struct sdio_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + return priv->cdstatus; } @@ -1894,10 +1896,10 @@ static int stm32_attach(struct sdio_dev_s *dev) * interrupt flags */ - sdmmc_putreg32(priv, STM32_SDMMC_MASK_RESET, - STM32_SDMMC_MASK_OFFSET); - sdmmc_putreg32(priv, STM32_SDMMC_ICR_STATICFLAGS, - STM32_SDMMC_ICR_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_MASK_RESET, + STM32_SDMMC_MASK_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_ICR_STATICFLAGS, + STM32_SDMMC_ICR_OFFSET); /* Enable SDIO interrupts at the NVIC. They can now be enabled at * the SDIO controller as needed. @@ -1947,23 +1949,23 @@ static int stm32_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, switch (cmd & MMCSD_RESPONSE_MASK) { - case MMCSD_NO_RESPONSE: - regval |= STM32_SDMMC_CMD_NORESPONSE; - break; - - case MMCSD_R1_RESPONSE: - case MMCSD_R1B_RESPONSE: - case MMCSD_R3_RESPONSE: - case MMCSD_R4_RESPONSE: - case MMCSD_R5_RESPONSE: - case MMCSD_R6_RESPONSE: - case MMCSD_R7_RESPONSE: - regval |= STM32_SDMMC_CMD_SHORTRESPONSE; - break; - - case MMCSD_R2_RESPONSE: - regval |= STM32_SDMMC_CMD_LONGRESPONSE; - break; + case MMCSD_NO_RESPONSE: + regval |= STM32_SDMMC_CMD_NORESPONSE; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R3_RESPONSE: + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + case MMCSD_R7_RESPONSE: + regval |= STM32_SDMMC_CMD_SHORTRESPONSE; + break; + + case MMCSD_R2_RESPONSE: + regval |= STM32_SDMMC_CMD_LONGRESPONSE; + break; } /* Set CPSMEN and the command index */ @@ -2175,31 +2177,31 @@ static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) switch (cmd & MMCSD_RESPONSE_MASK) { - case MMCSD_NO_RESPONSE: - events = STM32_SDMMC_CMDDONE_STA; - timeout = SDMMC_CMDTIMEOUT; - break; - - case MMCSD_R1_RESPONSE: - case MMCSD_R1B_RESPONSE: - case MMCSD_R2_RESPONSE: - case MMCSD_R6_RESPONSE: - events = STM32_SDMMC_RESPDONE_STA; - timeout = SDMMC_LONGTIMEOUT; - break; - - case MMCSD_R4_RESPONSE: - case MMCSD_R5_RESPONSE: - return -ENOSYS; - - case MMCSD_R3_RESPONSE: - case MMCSD_R7_RESPONSE: - events = STM32_SDMMC_RESPDONE_STA; - timeout = SDMMC_CMDTIMEOUT; - break; - - default: - return -EINVAL; + case MMCSD_NO_RESPONSE: + events = STM32_SDMMC_CMDDONE_STA; + timeout = SDMMC_CMDTIMEOUT; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R2_RESPONSE: + case MMCSD_R6_RESPONSE: + events = STM32_SDMMC_RESPDONE_STA; + timeout = SDMMC_LONGTIMEOUT; + break; + + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + return -ENOSYS; + + case MMCSD_R3_RESPONSE: + case MMCSD_R7_RESPONSE: + events = STM32_SDMMC_RESPDONE_STA; + timeout = SDMMC_CMDTIMEOUT; + break; + + default: + return -EINVAL; } /* Then wait for the response (or timeout) */ @@ -2208,9 +2210,9 @@ static int stm32_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) { if (--timeout <= 0) { - mcerr("ERROR: Timeout cmd: %08" PRIx32 - " events: %08" PRIx32 " STA: %08" PRIx32 "\n", - cmd, events, sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET)); + mcerr("ERROR: Timeout cmd: %08" PRIx32 + " events: %08" PRIx32 " STA: %08" PRIx32 "\n", + cmd, events, sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET)); return -ETIMEDOUT; } @@ -2445,6 +2447,7 @@ static int stm32_recvnotimpl(struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | STM32_SDMMC_CMDDONE_ICR, STM32_SDMMC_ICR_OFFSET); return -ENOSYS; @@ -2516,7 +2519,7 @@ static void stm32_waitenable(struct sdio_dev_s *dev, /* Enable event-related interrupts */ - sdmmc_putreg32(priv, STM32_SDMMC_WAITALL_ICR, STM32_SDMMC_ICR_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_WAITALL_ICR, STM32_SDMMC_ICR_OFFSET); } stm32_configwaitints(priv, waitmask, eventset, 0); @@ -2984,10 +2987,10 @@ static void stm32_callback(void *arg) { /* Yes.. queue it */ - mcinfo("Queuing callback to %p(%p)\n", - priv->callback, priv->cbarg); - work_queue(HPWORK, &priv->cbwork, priv->callback, - priv->cbarg, 0); + mcinfo("Queuing callback to %p(%p)\n", + priv->callback, priv->cbarg); + work_queue(HPWORK, &priv->cbwork, priv->callback, + priv->cbarg, 0); } else {
