maxikrie opened a new pull request, #20933:
URL: https://github.com/apache/nuttx/pull/20933
arch/xtensa/esp32s3: Set the MSPI clock when flash tuning is off.
## Summary
* Why: on the ESP32-S3, `CONFIG_ESP32S3_FLASH_FREQ_*` does not set the
clock code is fetched at unless flash timing tuning is compiled in.
* What: `arch/xtensa/src/esp32s3/esp32s3_spi_timing.c`.
* How: `esp32s3_spi_timing_set_mspi_flash_tuning()` programmed the
SPI0/SPI1 clocks (`esp32s3_spi_timing_set_mspi_high_speed()`) only at the
end of tuning, which is compiled in only for DTR or for STR above 80 MHz.
Otherwise the function was empty and SPI0, which fills the instruction
cache, kept the clock the bootloader left. Simple boot sets it from the
app image header, so it matches; with MCUboot it is MCUboot's own flash
frequency. Octal PSRAM init already calls
`esp32s3_spi_timing_set_mspi_high_speed()` unconditionally. This PR:
* calls `esp32s3_spi_timing_set_mspi_high_speed()` whether or not tuning
ran;
* skips its PSRAM clock write when no PSRAM is configured
(`PSRAM_CLOCK_DIVIDER` is 0), which would otherwise write garbage to
`SPI_MEM_SRAM_CLK_REG`.
* A second, whitespace-only commit fixes the existing nxstyle errors in the
same file, as required for modified files.
## Impact
* Is new feature added? Is existing feature changed? NO.
* Impact on user (will user need to adapt to change)? NO.
* Impact on build (will build process change)? NO.
* Impact on hardware (will arch(s) / board(s) / driver(s) change)? YES,
ESP32-S3 builds without timing tuning whose bootloader configured a
different flash frequency (typically MCUboot): SPI0 now runs at
`CONFIG_ESP32S3_FLASH_FREQ`. Simple-boot builds get the clock they
already had. Builds with tuning or octal PSRAM are unchanged.
* Impact on documentation (is update required / provided)? NO.
* Impact on security (any sort of implications)? NO.
* Impact on compatibility (backward/forward/interoperability)? NO.
## Testing
I confirm that changes are verified on local setup and works as intended:
* Build Host(s): Debian Linux (kernel 6.1), x86_64,
`xtensa-esp-elf-gcc (crosstool-NG esp-14.2.0_20241119) 14.2.0`.
* Target(s): xtensa, `esp32s3-devkit:nsh`, `esp32s3-devkit:psram_quad`,
`esp32s3-devkit:psram_octal`, `esp32s3-devkit:mcuboot_nsh` (build);
custom ESP32-S3 board, no PSRAM, QIO flash, MCUboot built at 40 MHz,
app at 80 MHz (runtime).
* Reproduce: boot an app configured for 80 MHz flash through an MCUboot
built for 40 MHz, with `CONFIG_BENCHMARK_COREMARK=y`, and run `coremark`
from NSH with and without this change.
Build:
```
$ for c in nsh psram_quad psram_octal mcuboot_nsh; do
./tools/configure.sh esp32s3-devkit:$c && make -j EXTRAFLAGS=-Werror
make distclean; done
CC: chip/esp32s3_spi_timing.c
LD: nuttx
(no warnings or errors for any of the four)
$ ./tools/checkpatch.sh -g HEAD~2..HEAD
✔️ All checks pass.
```
## PR verification Self-Check
* [x] This PR introduces only one functional change.
* [x] I have updated all required description fields above.
* [x] My PR adheres to Contributing
[Guidelines](https://github.com/apache/nuttx/blob/master/CONTRIBUTING.md) and
[Documentation](https://nuttx.apache.org/docs/latest/contributing/index.html)
(git commit title and message, coding standard, etc).
* [ ] My PR is still work in progress (not ready for review).
* [x] My PR is ready for review and can be safely merged into a codebase.
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