daniel-p-carvalho opened a new pull request, #20965:
URL: https://github.com/apache/nuttx/pull/20965
## Summary
`STM32_FLASH_ICACHE`/`STM32_FLASH_DCACHE` exist only for F2/F4. The G4 RCC
leaves the caches at their reset value and the L4 RCC enables them
unconditionally. This makes the caches follow the same common options on G4 and
L4 as on F4 (all default `y`, so nothing changes by default):
1. Style: fix two `nxstyle` "Bad alignment" errors in the G4 RCC.
2. Select `STM32_HAVE_FLASH_{I,D}CACHE` on G4 and L4 and make their RCC set
`ICEN`/`DCEN` from the options.
3. With that, `STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW` becomes
selectable on G4, where it defaults to `y`. It was unreachable on G4, and on L4
since `0d4a9cf1c8` made it depend on `STM32_FLASH_DCACHE`, which L4 never had.
The driver now also disables the cache before the page erase and releases
`DCRST` after setting it (as the erratum asks).
Why: ES0430 erratum 2.2.2 (data cache corrupted when reading one bank while
writing the other, dual bank). On an STM32G474 an MCUboot swap/revert hit an
intermittent bus fault in `up_progmem_write()`.
## Impact
G4: the data cache is off during flash writes (small slowdown), caches stay
on otherwise. L4: the workaround option is selectable again; default stays `n`.
Other families unchanged.
## Testing
STM32G474 custom board, MCUboot loader running from bank 1, slots in both
banks. `FLASH_ACR` read over SWD with the CPU halted:
| Config | FLASH_ACR | Swap + revert runs |
|---|---|---|
| defaults | `0x704` (ICEN, DCEN, PRFTEN) | 8 / 8 OK |
| `DCACHE=n` | `0x304` | 4 / 4 OK |
| `ICACHE=n` | `0x504` | 2 / 2 OK |
Before: intermittent bus fault.
**Not tested on L4** (no hardware). The L4 RCC changes were built
(`nucleo-l476rg:nsh`, `nucleo-l496zg:nsh`, and L476 with both caches disabled)
and the options checked in the generated `.config`: they show up as `y`, and
the workaround is selectable (off) on L476/L496/L4R9 and not offered on single
bank L432/L452. `stm32l4_flash.c` and `stm32_flash_m3m4_f2f4.c` also leave
`DCRST` set after resetting the cache; I did not touch them.
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