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commit ad1e4a152300924fa27d9602be48669ce4e99734 Author: Daniel P. Carvalho <[email protected]> AuthorDate: Sat Oct 24 10:58:13 2026 -0300 arch/arm/src/common/stm32: make the flash caches configurable on G4 and L4 STM32_FLASH_ICACHE and STM32_FLASH_DCACHE only exist for STM32F2 and STM32F4. The G4 RCC leaves the caches at their reset value and the L4 RCC enables them unconditionally, so they cannot be turned off, and the options that depend on them (the data cache RWW workaround) are not selectable. Select STM32_HAVE_FLASH_ICACHE and STM32_HAVE_FLASH_DCACHE on G4 and L4, and make the G4 and L4 RCC set ICEN and DCEN from the options, as the F4 does. Both default to y, so the cache setup does not change. Tested on an STM32G474: FLASH_ACR reads 0x704 with the defaults, with DCEN clear for STM32_FLASH_DCACHE=n and with ICEN clear for STM32_FLASH_ICACHE=n. The L4 RCC changes were only built and the options checked in the generated .config (no L4 hardware available). Assisted-by: Claude Code:claude-sonnet-5-5 Signed-off-by: Daniel P. Carvalho <[email protected]> --- arch/arm/src/stm32g4/Kconfig | 2 ++ arch/arm/src/stm32g4/stm32g4xxxx_rcc.c | 16 +++++++++++----- arch/arm/src/stm32l4/Kconfig | 2 ++ arch/arm/src/stm32l4/stm32l4x5xx_rcc.c | 12 ++++++++---- arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 12 ++++++++---- arch/arm/src/stm32l4/stm32l4xrxx_rcc.c | 10 +++++++--- 6 files changed, 38 insertions(+), 16 deletions(-) diff --git a/arch/arm/src/stm32g4/Kconfig b/arch/arm/src/stm32g4/Kconfig index 743783550ea..cc5db2dd027 100644 --- a/arch/arm/src/stm32g4/Kconfig +++ b/arch/arm/src/stm32g4/Kconfig @@ -80,6 +80,8 @@ config STM32_STM32G4XXX default n select STM32_HAVE_DMA1 select STM32_HAVE_COMP + select STM32_HAVE_FLASH_ICACHE + select STM32_HAVE_FLASH_DCACHE select STM32_HAVE_DMA2 select ARCH_CORTEXM4 select ARCH_HAVE_FPU diff --git a/arch/arm/src/stm32g4/stm32g4xxxx_rcc.c b/arch/arm/src/stm32g4/stm32g4xxxx_rcc.c index cecaf32c066..28ded6ec96a 100644 --- a/arch/arm/src/stm32g4/stm32g4xxxx_rcc.c +++ b/arch/arm/src/stm32g4/stm32g4xxxx_rcc.c @@ -888,16 +888,22 @@ static void stm32_stdclockconfig(void) * to go into effect and enable prefetch to reduce latency due to * these wait states (ART accelerator). * - * REVISIT: Should we also enable I-Cache and D-Cache? Also, the - * reference manual suggests that we must read the ACR register to - * make sure the latency setting has taken effect. Are we doing that - * correctly? + * The instruction and data caches follow CONFIG_STM32_FLASH_ICACHE and + * CONFIG_STM32_FLASH_DCACHE. REVISIT: the reference manual suggests that + * we must read the ACR register to make sure the latency setting has taken + * effect. Are we doing that correctly? */ regval = getreg32(STM32_FLASH_ACR); - regval &= ~FLASH_ACR_LATENCY_MASK; + regval &= ~(FLASH_ACR_LATENCY_MASK | FLASH_ACR_ICEN | FLASH_ACR_DCEN); regval |= FLASH_ACR_LATENCY_SETTING; regval |= FLASH_ACR_PRFTEN; +#ifdef CONFIG_STM32_FLASH_ICACHE + regval |= FLASH_ACR_ICEN; +#endif +#ifdef CONFIG_STM32_FLASH_DCACHE + regval |= FLASH_ACR_DCEN; +#endif putreg32(regval, STM32_FLASH_ACR); while ((getreg32(STM32_FLASH_ACR) & FLASH_ACR_LATENCY_MASK) != diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index fd5e8d18e0b..c9bba70b782 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -11,6 +11,8 @@ config STM32_L4_PERIPHERALS bool default ARCH_CHIP_STM32L4 select STM32_HAVE_IP_DBGMCU_V4 + select STM32_HAVE_FLASH_ICACHE + select STM32_HAVE_FLASH_DCACHE select STM32_HAVE_DAC1 select STM32_HAVE_DMA1 select STM32_HAVE_DMA2 diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index 254efbeb45b..29acb81978d 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -851,11 +851,15 @@ static void stm32_stdclockconfig(void) * and 4 wait states */ + regval = FLASH_ACR_LATENCY_4; +#ifdef CONFIG_STM32_FLASH_ICACHE + regval |= FLASH_ACR_ICEN; +#endif +#ifdef CONFIG_STM32_FLASH_DCACHE + regval |= FLASH_ACR_DCEN; +#endif #ifdef CONFIG_STM32_FLASH_PREFETCH - regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | - FLASH_ACR_PRFTEN); -#else - regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); + regval |= FLASH_ACR_PRFTEN; #endif putreg32(regval, STM32_FLASH_ACR); diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index 7e2aedd4736..b9acbb8aa90 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -683,11 +683,15 @@ static void stm32_stdclockconfig(void) * and freq */ + regval = FLASH_ACR_LATENCY_4; +#ifdef CONFIG_STM32_FLASH_ICACHE + regval |= FLASH_ACR_ICEN; +#endif +#ifdef CONFIG_STM32_FLASH_DCACHE + regval |= FLASH_ACR_DCEN; +#endif #ifdef CONFIG_STM32_FLASH_PREFETCH - regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | - FLASH_ACR_PRFTEN); -#else - regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); + regval |= FLASH_ACR_PRFTEN; #endif putreg32(regval, STM32_FLASH_ACR); diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c index e3a42befec0..e7c0179e4e7 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c @@ -927,10 +927,14 @@ static void stm32_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache and data cache */ +#ifdef CONFIG_STM32_FLASH_ICACHE + regval |= FLASH_ACR_ICEN; +#endif +#ifdef CONFIG_STM32_FLASH_DCACHE + regval |= FLASH_ACR_DCEN; +#endif #ifdef CONFIG_STM32_FLASH_PREFETCH - regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); -#else - regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN); + regval |= FLASH_ACR_PRFTEN; #endif putreg32(regval, STM32_FLASH_ACR);
