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new 90b00f7aba9 arch/arm/src/stm32: Add Kconfig to support SD high-speed
90b00f7aba9 is described below
commit 90b00f7aba96d35ab0cf3e0bf2de35ff36644bb0
Author: Peter Barada <[email protected]>
AuthorDate: Wed Oct 28 15:27:51 2026 -0400
arch/arm/src/stm32: Add Kconfig to support SD high-speed
Add CONFIG_STM32_SDMMC1/2_SD_HS_MODE which if enabled (and
corresponding STM32_SDMMC_SDXFR_HS_CLKDIV is defined in board.h)
then after generic MMC/SD driver switches to 4-bit mode and card
supports high-speed, switch SD clk to 50Mhz.
Signed-off-by Peter Barada <[email protected]>
---
arch/arm/src/common/stm32/Kconfig.sdio | 24 ++++++++++++++
arch/arm/src/stm32h7/stm32_sdmmc.c | 59 +++++++++++++++++++++++++++-------
2 files changed, 71 insertions(+), 12 deletions(-)
diff --git a/arch/arm/src/common/stm32/Kconfig.sdio
b/arch/arm/src/common/stm32/Kconfig.sdio
index d5305a6adc9..0811d916ba3 100644
--- a/arch/arm/src/common/stm32/Kconfig.sdio
+++ b/arch/arm/src/common/stm32/Kconfig.sdio
@@ -120,6 +120,18 @@ config SDMMC1_WIDTH_D1_ONLY
---help---
Select 1-bit transfer mode. Default: 4-bit transfer mode.
+config SDMMC1_SD_HS_MODE
+ bool "Support SD card high speed mode on SDMMC1"
+ depends on STM32_SDMMC1
+ default n
+ ---help---
+ Report SDIO_CAPS_SD_HS_MODE for SDMMC1 so that the
+ generic MMC/SD driver switches an inserted SD card
+ into high speed mode (CMD6) and raises the bus clock
+ accordingly, once the card confirms the switch. The
+ board must provide STM32_SDMMC_SDXFR_HS_CLKDIV in
+ board.h for the higher clock.
+
config SDMMC1_SDIO_MODE
bool "SDIO Card Support"
depends on STM32_COMMON_F7_H7_H5 && STM32_SDMMC && STM32_SDMMC1
@@ -142,6 +154,18 @@ config SDMMC2_WIDTH_D1_ONLY
---help---
Select 1-bit transfer mode. Default: 4-bit transfer mode.
+config SDMMC2_SD_HS_MODE
+ bool "Support SD card high speed mode on SDMMC2"
+ depends on STM32_SDMMC2
+ default n
+ ---help---
+ Report SDIO_CAPS_SD_HS_MODE for SDMMC2 so that the
+ generic MMC/SD driver switches an inserted SD card
+ into high speed mode (CMD6) and raises the bus clock
+ accordingly, once the card confirms the switch. The
+ board must provide STM32_SDMMC_SDXFR_HS_CLKDIV in
+ board.h for the higher clock.
+
config SDMMC2_SDIO_MODE
bool "SDIO Card Support"
depends on STM32_COMMON_F7_H7_H5 && STM32_SDMMC && STM32_SDMMC2
diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c
b/arch/arm/src/stm32h7/stm32_sdmmc.c
index d84ced38b2d..a258fa79102 100644
--- a/arch/arm/src/stm32h7/stm32_sdmmc.c
+++ b/arch/arm/src/stm32h7/stm32_sdmmc.c
@@ -238,14 +238,21 @@
* This condition breaks interrupts delivering mechanism over DAT[1]/IRQ
* SDIO line to the host.
*/
-# define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \
- STM32_SDMMC_CLKCR_EDGE | \
+# define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \
+ STM32_SDMMC_CLKCR_EDGE | \
STM32_SDMMC_CLKCR_WIDBUS_D4)
+# define STM32_SDMMC_CLCKR_SDWIDEXFR_HS (STM32_SDMMC_SDXFR_HS_CLKDIV | \
+ STM32_SDMMC_CLKCR_EDGE | \
+ STM32_SDMMC_CLKCR_WIDBUS_D4)
#else
-# define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \
- STM32_SDMMC_CLKCR_EDGE | \
- STM32_SDMMC_CLKCR_PWRSAV | \
+# define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \
+ STM32_SDMMC_CLKCR_EDGE | \
+ STM32_SDMMC_CLKCR_PWRSAV | \
STM32_SDMMC_CLKCR_WIDBUS_D4)
+# define STM32_SDMMC_CLCKR_SDWIDEXFR_HS (STM32_SDMMC_SDXFR_HS_CLKDIV | \
+ STM32_SDMMC_CLKCR_EDGE | \
+ STM32_SDMMC_CLKCR_PWRSAV | \
+ STM32_SDMMC_CLKCR_WIDBUS_D4)
#endif
/* Timing */
@@ -394,6 +401,7 @@ struct stm32_dev_s
bool widebus; /* Required for DMA support */
bool onebit; /* true: Only 1-bit transfers are
supported */
+ bool highspeed; /* true: Support high-speed mode(CMD6) */
#if defined(HAVE_SDMMC_SDIO_MODE)
/* Interrupt at SDIO_D1 pin, only for SDIO cards */
@@ -2168,6 +2176,11 @@ static sdio_capset_t stm32_capabilities(struct
sdio_dev_s *dev)
caps |= SDIO_CAPS_4BIT;
}
+ if (priv->highspeed)
+ {
+ caps |= SDIO_CAPS_SD_HS_MODE;
+ }
+
caps |= SDIO_CAPS_DMABEFOREWRITE;
#if defined(CONFIG_STM32_SDMMC_IDMA)
@@ -2317,6 +2330,16 @@ static void stm32_clock(struct sdio_dev_s *dev, enum
sdio_clock_e rate)
case CLOCK_SD_TRANSFER_1BIT:
clckr = STM32_SDMMC_CLCKR_SDXFR;
break;
+
+ /* SD high speed */
+
+ case CLOCK_SD_TRANSFER_4BIT_HS:
+#if defined(CONFIG_SDMMC1_SD_HS_MODE) || defined(CONFIG_SDMMC2_SD_HS_MODE)
+ clckr = STM32_SDMMC_CLCKR_SDWIDEXFR_HS;
+#else
+ clckr = STM32_SDMMC_CLCKR_SDXFR;
+#endif
+ break;
}
/* Set the new clock frequency along with the clock enable/disable bit */
@@ -3814,11 +3837,17 @@ struct sdio_dev_s *sdio_initialize(int slotno)
priv = &g_sdmmcdev1;
-#if defined(CONFIG_SDMMC1_WIDTH_D1_ONLY)
+# if defined(CONFIG_SDMMC1_WIDTH_D1_ONLY)
priv->onebit = true;
-#else
+# else
priv->onebit = false;
-#endif
+# endif
+
+# if defined(CONFIG_SDMMC1_SD_HS_MODE)
+ priv->highspeed = true;
+# else
+ priv->highspeed = false;
+# endif
/* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable
* of 8-bit wide bus operation but D4-D7 are not configured).
@@ -3827,16 +3856,16 @@ struct sdio_dev_s *sdio_initialize(int slotno)
* utility in the scope of the board support package.
*/
-#ifndef CONFIG_SDIO_MUXBUS
+# ifndef CONFIG_SDIO_MUXBUS
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0));
-# ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY
+# ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D1));
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D2));
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_D3));
-# endif
+# endif
stm32_configgpio(GPIO_SDMMC1_CK);
stm32_configgpio(SDMMC1_SDIO_PULL(GPIO_SDMMC1_CMD));
-#endif
+# endif
}
else
#endif
@@ -3853,6 +3882,12 @@ struct sdio_dev_s *sdio_initialize(int slotno)
priv->onebit = false;
# endif
+# if defined(CONFIG_SDMMC2_SD_HS_MODE)
+ priv->highspeed = true;
+# else
+ priv->highspeed = false;
+# endif
+
/* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable
* of 8-bit wide bus operation but D4-D7 are not configured).
*
