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The following commit(s) were added to refs/heads/master by this push:
new 2225887e215 arch/arm64/goldfish: align chip.h definitions with qemu
chip.h
2225887e215 is described below
commit 2225887e21573062566e067335d7f077ed47b6a2
Author: hujun5 <[email protected]>
AuthorDate: Sat Mar 28 14:38:55 2026 +0800
arch/arm64/goldfish: align chip.h definitions with qemu chip.h
Add missing memory region definitions to goldfish/chip.h that are
required by the shared linker script dramboot_armv8a.ld:
- CONFIG_SHMEM_BASEADDR / CONFIG_SHMEM_SIZE for shared memory region
- CONFIG_QEMU_DRAM_BASE for QEMU DRAM base address
- CONFIG_SECURE_MEM_BASEADDR / CONFIG_SECURE_MEM_SIZE for TrustZone
- CONFIG_RAMBANK1_ADDR / CONFIG_RAMBANK1_SIZE with TrustZone support
- CONFIG_LOAD_BASE now supports both secure and non-secure boot
Previously, building goldfish-arm64-v8a-ap_test failed at link time
because dramboot_armv8a.ld includes <arch/qemu/chip.h> which guards
all definitions under CONFIG_ARCH_CHIP_QEMU_ARM64, but goldfish
defines CONFIG_ARCH_CHIP_GOLDFISH_ARM64 instead, leaving
CONFIG_LOAD_BASE and CONFIG_SHMEM_BASEADDR undefined.
Signed-off-by: hujun5 <[email protected]>
---
arch/arm64/include/goldfish/chip.h | 73 +++++++++++++++++++++++++++++++-------
1 file changed, 60 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/include/goldfish/chip.h
b/arch/arm64/include/goldfish/chip.h
index f6b3ae2cb84..b6e84d35826 100644
--- a/arch/arm64/include/goldfish/chip.h
+++ b/arch/arm64/include/goldfish/chip.h
@@ -57,28 +57,75 @@
*/
#if CONFIG_ARM64_GIC_VERSION == 2
-#define CONFIG_GICD_BASE 0x8000000
-#define CONFIG_GICR_BASE 0x8010000
+#define CONFIG_GICD_BASE 0x8000000
+#define CONFIG_GICR_BASE 0x8010000
#elif CONFIG_ARM64_GIC_VERSION == 3 || CONFIG_ARM64_GIC_VERSION == 4
-#define CONFIG_GICD_BASE 0x8000000
-#define CONFIG_GICR_BASE 0x80a0000
-#define CONFIG_GICR_OFFSET 0x20000
+#define CONFIG_GICD_BASE 0x8000000
+#define CONFIG_GICR_BASE 0x80a0000
+#define CONFIG_GICR_OFFSET 0x20000
#else
#error CONFIG_ARM64_GIC_VERSION should be 2, 3 or 4
#endif /* CONFIG_ARM64_GIC_VERSION */
-#define CONFIG_FLASH_BASEADDR 0x7000000
-#define CONFIG_FLASH_SIZE MB(128)
+#define CONFIG_FLASH_BASEADDR 0x7000000
+#define CONFIG_FLASH_SIZE MB(128)
-#define CONFIG_DEVICEIO_BASEADDR 0x08000000
-#define CONFIG_DEVICEIO_SIZE MB(512)
+#define CONFIG_QEMU_DRAM_BASE 0x40000000
-#define CONFIG_RAM_ADDR 0x40000000
-#define CONFIG_RAM_SIZE MB(128)
+#define CONFIG_SECURE_MEM_BASEADDR 0x0e000000
+#define CONFIG_SECURE_MEM_SIZE MB(16)
-#define CONFIG_LOAD_BASE 0x40280000
+#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
+# define CONFIG_RAMBANK1_ADDR CONFIG_SECURE_MEM_BASEADDR
+# define CONFIG_RAMBANK1_SIZE CONFIG_SECURE_MEM_SIZE
+#else
+/* QEMU virt machine physical RAM always starts at 0x40000000.
+ * RAMBANK1 must cover from physical RAM base through the end of
+ * NuttX's configured RAM region (CONFIG_RAM_START + CONFIG_RAM_SIZE)
+ * so that the MMU mapping is large enough.
+ *
+ * When CONFIG_RAM_START > 0x40000000 (e.g. running under a hypervisor),
+ * the RAMBANK1 mapping still starts at 0x40000000 to keep the DTB
+ * accessible, and extends to cover CONFIG_RAM_END.
+ *
+ * The user must ensure QEMU is launched with enough RAM via -m option:
+ * -m <size> where size >=
+ * (CONFIG_RAM_START - 0x40000000 + CONFIG_RAM_SIZE)
+ */
+
+# define CONFIG_RAMBANK1_ADDR CONFIG_QEMU_DRAM_BASE
+# define CONFIG_RAMBANK1_SIZE (CONFIG_RAM_START - CONFIG_RAMBANK1_ADDR + \
+ CONFIG_RAM_SIZE)
+#endif
+#define CONFIG_DEVICEIO_BASEADDR 0x08000000
+#define CONFIG_DEVICEIO_SIZE MB(512)
+
+#define CONFIG_RAM_ADDR 0x40000000
+#define CONFIG_RAM_SIZE MB(128)
+
+#define CONFIG_SHMEM_BASEADDR 0x45000000
+#define CONFIG_SHMEM_SIZE MB(1)
+
+#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
+/* When booting via TF-A (Trusted Firmware-A), BL2 and BL31 occupy the
+ * secure SRAM region starting at 0x0e000000:
+ *
+ * 0x0e000000 - 0x0e001000 : Shared RAM (mailbox)
+ * 0x0e05b000 - 0x0e090000 : BL2 (212KB)
+ * 0x0e090000 - 0x0e100000 : BL31 (448KB)
+ *
+ * BL31 remains resident at runtime, so NuttX must be placed above
+ * 0x0e100000 (secure DRAM) to avoid overwriting BL31 code and data.
+ */
+
+# define CONFIG_LOAD_BASE (CONFIG_SECURE_MEM_BASEADDR + 0x100000)
+#else
+/* Load base is 0x280000 (2.5MB) offset from CONFIG_RAM_START */
+
+# define CONFIG_LOAD_BASE (CONFIG_RAM_START + 0x280000)
+#endif
-#define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xff)
+#define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xff)
#endif
