hujun260 opened a new pull request, #21753:
URL: https://github.com/apache/nuttx/pull/21753
# NuttX PR Description
## Title
arch/arm64: release virtual timer IRQ for non-secure Linux REE
## Description
This PR releases the ARM64 virtual timer interrupt for a non-secure Linux REE
running at EL1NS without EL2.
## Problem
The ARM64 one-shot timer initialization previously released only the
non-secure
physical timer interrupt (`GIC_IRQ_PTM`) from Group 1 Secure. This is
sufficient
for a NuttX non-secure world that uses the non-secure physical timer.
A Linux REE running at EL1NS without EL2 selects the virtual timer instead:
```text
arch_timer_select_ppi(): no hyp mode -> ARCH_TIMER_VIRT_PPI
```
If `GIC_IRQ_VTM` remains in Group 1 Secure, Linux does not receive virtual
timer
interrupts. As a result, Linux cannot sleep correctly, timer callbacks do not
fire, and the system only makes progress while busy-spinning.
## Changes
- Release `GIC_IRQ_VTM` from Group 1 Secure during per-CPU timer
initialization.
- Keep releasing `GIC_IRQ_PTM` for the NuttX non-secure-world timer path.
- Allow non-secure Linux running at EL1NS without EL2 to receive virtual
timer
ticks.
- Preserve the existing TrustZone timer routing for secure and non-secure
NuttX
configurations.
## Motivation
Ensure that both NuttX non-secure worlds and Linux non-secure REE systems can
receive the timer interrupt selected by their execution environment.
## Runtime Testing
The following runtime log was captured from the Vela QEMU ARM64 TrustZone
environment using the `qemu-arm64-v8a-ap` configuration:
- CPU: Cortex-A53
- SMP: 4 CPUs
- Memory: 1057 MiB
- Shared memory: 4 MiB ivshmem region
- GDB server: TCP port `7775`
### Trusted Firmware-A and BL32 initialization
```text
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.14.0(debug):fb1381d84
INFO: BL2: Loading image id 4
INFO: Handoff to BL32
NOTICE: BL31: Initializing runtime services
INFO: NUTTXSPD: BL32 ep=0xe100000
INFO: NUTTXSPD: BL32 CPU0 entry done
INFO: NUTTXSPD: BL32 CPU1 entry done
INFO: NUTTXSPD: BL32 CPU2 entry done
INFO: NUTTXSPD: BL32 CPU3 entry done
INFO: Entry point address = 0x40280000
```
### AP and TEE initialization
```text
0.382308 8 I 0 ap pci_sdhci_probe: SDHCI controller at 10001000 irq=37
0.383143 8 I 0 ap pci_ivshmem_probe: shmem addr=0x8000400000 size=4194304
reg=0x10001100
0.393617 8 I 0 ap board_init_emmc: GPT partitions registered
NuttX 12.7.2 arm64 ap
21 I 0 tee D/TC:0 21 call_initcalls:40 level 1 register_time_source()
21 I 0 tee D/TC:0 21 call_initcalls:40 level 3 tee_cryp_init()
21 I 0 tee D/TC:0 21 call_initcalls:40 level 4 host_fs_init()
21 I 0 tee D/TC:0 21 host_fs_init:162 host fs init success
21 I 0 tee D/TC:0 21 call_initcalls:40 level 6 default_mobj_init()
```
### AP-side `ostest`
```text
qemu-armv8a-ap> ostest
...
user_main: smp call test
cpu_call_test: Call cpu 0, wait
cpu_call_test: Call cpu 1, wait
cpu_call_test: Call cpu 2, wait
cpu_call_test: Call cpu 3, wait
cpu_call_test: Call multi cpu, wait
cpu_call_test: Test success
user_main: Exiting
ostest_main: Exiting with status 0
```
### TEE-side `ostest`
```text
tee> ostest
...
user_main: smp call test
cpu_call_test: Call cpu 0, wait
cpu_call_test: Call cpu 1, wait
cpu_call_test: Call cpu 2, wait
cpu_call_test: Call cpu 3, wait
cpu_call_test: Call multi cpu, wait
cpu_call_test: Test success
user_main: Exiting
ostest_main: Exiting with status 0
```
## Testing Status
- [ ] Compile-tested with the Linux REE EL1NS/no-EL2 configuration
- [ ] Verified Linux timer interrupts and sleep behavior directly
- [x] Runtime-tested on Vela QEMU ARM64 TrustZone
- [x] BL32 initialized on all four CPUs
- [x] AP-side `ostest` completed with status 0
- [x] TEE-side `ostest` completed with status 0
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