casaroli commented on code in PR #21732:
URL: https://github.com/apache/nuttx/pull/21732#discussion_r4549287054
##########
arch/arm64/src/common/arm64_perf.c:
##########
@@ -68,28 +52,13 @@ void up_perf_init(void *arg)
pmu_clucntr_irq_disable(CLUSTERPMINTENCLR_EL1_C);
pmu_clucntr_enable(CLUSTERPMCNTENSET_EL1_C);
#else
- arm64_perf_start();
-#endif
-}
-
-/****************************************************************************
- * Name: arm64_perf_secondary_init
- *
- * Description:
- * Start the cycle counter of a secondary CPU. up_perf_init() runs on
- * the boot CPU only, and the cycle counter is a register of each CPU.
- * The cluster PMU is common to the CPUs: it is already started.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_SMP
-void arm64_perf_secondary_init(void)
Review Comment:
With SMP the PMU perf code is no longer built (ARCH_HAVE_PERF_EVENTS is off
unless ARCH_CLUSTER_PMU is on), and with the cluster PMU
arm64_perf_secondary_init() was empty, so no build calls it to do anything.
##########
arch/arm64/Kconfig:
##########
@@ -381,7 +381,7 @@ config ARCH_CORTEX_R82
select ARCH_HAVE_FPU
select ARCH_HAVE_CLUSTER_PMU
select ARM64_HAVE_NEON
- select ARCH_HAVE_PERF_EVENTS_USER_ACCESS if !ARCH_CLUSTER_PMU
+ select ARCH_HAVE_PERF_EVENTS_USER_ACCESS if !SMP && !ARCH_CLUSTER_PMU
Review Comment:
ARCH_HAVE_PERF_EVENTS_USER_ACCESS selects ARCH_HAVE_PERF_EVENTS, so without
!SMP a Cortex-R82 SMP build would use the per-CPU PMU cycle counter again
instead of the arch timer.
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