gustavonihei commented on a change in pull request #3126: URL: https://github.com/apache/incubator-nuttx/pull/3126#discussion_r600512854
########## File path: arch/risc-v/src/esp32c3/rom/esp32c3_spiflash.h ########## @@ -0,0 +1,826 @@ +/***************************************************************************** + * arch/risc-v/src/esp32c3/rom/esp32c3_spiflash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +#ifndef _ROM_SPI_FLASH_H_ +#define _ROM_SPI_FLASH_H_ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include <stdint.h> +#include <stdbool.h> + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* spi_flash_apis, spi flash operation related apis */ + +/***************************************************************************** + * Note + ***************************************************************************** + * 1. ESP32C3 chip have 4 SPI slave/master, however, SPI0 is + * used as an SPI master to access Flash and ext-SRAM by + * Cache module. It will support Decryto read for Flash, + * read/write for ext-SRAM. And SPI1 is also used as an + * SPI master for Flash read/write and ext-SRAM read/write. + * It will support Encrypto write for Flash. + * 2. As an SPI master, SPI support Highest clock to 80M, + * however, Flash with 80M Clock should be configured + * for different Flash chips. If you want to use 80M + * clock We should use the SPI that is certified by + * Espressif. However, the certification is not started + * at the time, so please use 40M clock at the moment. + * 3. SPI Flash can use 2 lines or 4 lines mode. If you + * use 2 lines mode, you can save two pad SPIHD and + * SPIWP for gpio. ESP32C3 support configured SPI pad for + * Flash, the configuration is stored in efuse and flash. + * However, the configurations of pads should be certified + * by Espressif. If you use this function, please use 40M + * clock at the moment. + * 4. ESP32C3 support to use Common SPI command to configure + * Flash to QIO mode, if you failed to configure with fix + * command. With Common SPI Command, ESP32C3 can also provide + * a way to use same Common SPI command groups on different + * Flash chips. Review comment: ```suggestion * 1. ESP32-C3 chip have 4 SPI slave/master, however, SPI0 is * used as an SPI master to access Flash and ext-SRAM by * Cache module. It will support Decryto read for Flash, * read/write for ext-SRAM. And SPI1 is also used as an * SPI master for Flash read/write and ext-SRAM read/write. * It will support Encrypto write for Flash. * 2. As an SPI master, SPI support Highest clock to 80M, * however, Flash with 80M Clock should be configured * for different Flash chips. If you want to use 80M * clock We should use the SPI that is certified by * Espressif. However, the certification is not started * at the time, so please use 40M clock at the moment. * 3. SPI Flash can use 2 lines or 4 lines mode. If you * use 2 lines mode, you can save two pad SPIHD and * SPIWP for gpio. ESP32-C3 support configured SPI pad for * Flash, the configuration is stored in efuse and flash. * However, the configurations of pads should be certified * by Espressif. If you use this function, please use 40M * clock at the moment. * 4. ESP32-C3 support to use Common SPI command to configure * Flash to QIO mode, if you failed to configure with fix * command. With Common SPI Command, ESP32C3 can also provide * a way to use same Common SPI command groups on different * Flash chips. ``` Only fixing the missing hyphen the ESP32-C3. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. For queries about this service, please contact Infrastructure at: [email protected]
